XRSTOR—Restore Processor Extended StatesInstruction Operand EncodingDescriptionPerforms a full or partial restore of processor state components from the XSAVE area located at the memory address specified by the source operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The specific state components restored correspond to the bits set in the requested-feature bitmap (RFBM), which is the logical-AND of EDX:EAX and XCR0.The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of Intel® 64 and IA-32 Architectures Soft-ware Developer’s Manual, Volume 1. Like FXRSTOR and FXSAVE, the memory format used for x87 state depends on a REX.W prefix; see Section 13.5.1, “x87 State” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.Section 13.8, “Operation of XRSTOR,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 provides a detailed description of the operation of the XRSTOR instruction. The following items provide a high-level outline:•Execution of XRSTOR may take one of two forms: standard and compacted. Bit63 of the XCOMP_BV field in the XSAVE header determines which form is used: value 0 specifies the standard form, while value 1 specifies the compacted form.•If RFBM[i]= 0, XRSTOR does not update state component i.1•If RFBM[i]= 1 and biti is clear in the XSTATE_BV field in the XSAVE header, XRSTOR initializes state component i.•If RFBM[i]= 1 and XSTATE_BV[i]= 1, XRSTOR loads state componenti from the XSAVE area.•The standard form of XRSTOR treats MXCSR (which is part of state component 1 — SSE) differently from the XMM registers. If either form attempts to load MXCSR with an illegal value, a general-protection exception (#GP) occurs.•XRSTOR loads the internal value XRSTOR_INFO, which may be used to optimize a subsequent execution of XSAVEOPT or XSAVES.•Immediately following an execution of XRSTOR, the processor tracks as in-use (not in initial configuration) any state componenti for which RFBM[i]= 1 and XSTATE_BV[i]= 1; it tracks as modified any state component ifor which RFBM[i]= 0.Use of a source operand not aligned to 64-byte boundary (for 64-bit and 32-bit modes) results in a general-protec-tion (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.See Section 13.6, “Processor Tracking of XSAVE-Managed State,” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 for discussion of the bitmaps XINUSE and XMODIFIED and of the quantity XRSTOR_INFO.Opcode /InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescriptionNP 0F AE /5XRSTOR memMV/VXSAVERestore state components specified by EDX:EAX from mem.NP REX.W + 0F AE /5XRSTOR64 memMV/N.E.XSAVERestore state components specified by EDX:EAX from mem.Op/EnOperand 1Operand 2Operand 3Operand 4MModRM:r/m (r)NANANA1.There is an exception if RFBM[1]= 0 and RFBM[2]= 1. In this case, the standard form of XRSTOR will load MXCSR from memory, even though MXCSR is part of state component 1 — SSE. The compacted form of XRSTOR does not make this exception.
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