image/svg+xmlXOR—Logical Exclusive ORInstruction Operand EncodingDescriptionPerforms a bitwise exclusive OR (XOR) operation on the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory oper-ands cannot be used in one instruction.) Each bit of the result is 1 if the corresponding bits of the operands are different; each bit is 0 if the corresponding bits are the same.This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.OpcodeInstructionOp/ En64-Bit ModeCompat/Leg ModeDescription34 ibXOR AL, imm8IValidValidAL XOR imm8.35 iwXOR AX, imm16IValidValidAX XOR imm16.35 idXOR EAX, imm32IValidValidEAX XOR imm32.REX.W + 35 idXOR RAX, imm32IValidN.E.RAX XOR imm32 (sign-extended).80 /6 ibXOR r/m8, imm8MIValidValidr/m8 XOR imm8.REX + 80 /6 ibXOR r/m8*, imm8MIValidN.E.r/m8 XOR imm8.81 /6 iwXOR r/m16, imm16MIValidValidr/m16 XOR imm16.81 /6 idXOR r/m32, imm32MIValidValidr/m32 XOR imm32.REX.W + 81 /6 idXOR r/m64, imm32MIValidN.E.r/m64 XOR imm32 (sign-extended).83 /6 ibXOR r/m16, imm8MIValidValidr/m16 XOR imm8 (sign-extended).83 /6 ibXOR r/m32, imm8MIValidValidr/m32 XOR imm8 (sign-extended).REX.W + 83 /6 ibXOR r/m64, imm8MIValidN.E.r/m64 XOR imm8 (sign-extended).30 /rXOR r/m8, r8MRValidValidr/m8 XOR r8.REX + 30 /rXOR r/m8*, r8*MRValidN.E.r/m8 XOR r8.31 /rXOR r/m16, r16MRValidValidr/m16 XOR r16.31 /rXOR r/m32, r32MRValidValidr/m32 XOR r32.REX.W + 31 /rXOR r/m64, r64MRValidN.E.r/m64 XOR r64.32 /rXOR r8, r/m8RMValidValidr8 XOR r/m8.REX + 32 /rXOR r8*, r/m8*RMValidN.E.r8 XOR r/m8.33 /rXOR r16, r/m16RMValidValidr16 XOR r/m16.33 /rXOR r32, r/m32RMValidValidr32 XOR r/m32.REX.W + 33 /rXOR r64, r/m64RMValidN.E.r64 XOR r/m64.NOTES:*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. Op/EnOperand 1Operand 2Operand 3Operand 4IAL/AX/EAX/RAXimm8/16/32NANAMIModRM:r/m (r, w)imm8/16/32NANAMRModRM:r/m (r, w)ModRM:reg (r)NANARMModRM:reg (r, w)ModRM:r/m (r)NANA

image/svg+xmlIn 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.OperationDEST := DEST XOR SRC;Flags AffectedThe OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is undefined.Protected Mode Exceptions#GP(0)If the destination operand points to a non-writable segment.If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used but the destination is not a memory operand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used but the destination is not a memory operand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made.#UD If the LOCK prefix is used but the destination is not a memory operand.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used but the destination is not a memory operand.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.