XEND — Transactional EndInstruction Operand EncodingDescriptionThe instruction marks the end of an RTM code region. If this corresponds to the outermost scope (that is, including this XEND instruction, the number of XBEGIN instructions is the same as number of XEND instructions), the logical processor will attempt to commit the logical processor state atomically. If the commit fails, the logical processor will rollback all architectural register and memory updates performed during the RTM execution. The logical processor will resume execution at the fallback address computed from the outermost XBEGIN instruction. The EAX register is updated to reflect RTM abort information.XEND executed outside a transactional region will cause a #GP (General Protection Fault). OperationXENDIF (RTM_ACTIVE = 0) THENSIGNAL #GPELSERTM_NEST_COUNT--IF (RTM_NEST_COUNT = 0) THENTry to commit transactionIF fail to commit transactional executionTHENGOTO RTM_ABORT_PROCESSING;ELSE (* commit success *)RTM_ACTIVE:= 0FI;FI;FI;(* For any RTM abort condition encountered during RTM execution *)RTM_ABORT_PROCESSING:Restore architectural register stateDiscard memory updates performed in transactionUpdate EAX with statusRTM_NEST_COUNT := 0RTM_ACTIVE:= 0IF 64-bit ModeTHENRIP:= fallbackRIPELSEEIP:= fallbackEIPFI;ENDOpcode/InstructionOp/ En64/32bit Mode SupportCPUID Feature FlagDescriptionNP 0F 01 D5XENDAV/VRTMSpecifies the end of an RTM code region.Op/EnOperand 1Operand2Operand3Operand4ANANANANA
This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.