image/svg+xmlXCHG—Exchange Register/Memory with RegisterInstruction Operand EncodingDescriptionExchanges the contents of the destination (first) and source (second) operands. The operands can be two general-purpose registers or a register and a memory location. If a memory operand is referenced, the processor’s locking protocol is automatically implemented for the duration of the exchange operation, regardless of the presence or absence of the LOCK prefix or of the value of the IOPL. (See the LOCK prefix description in this chapter for more information on the locking protocol.)This instruction is useful for implementing semaphores or similar data structures for process synchronization. (See “Bus Locking” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information on bus locking.) The XCHG instruction can also be used instead of the BSWAP instruction for 16-bit operands.In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.OpcodeInstructionOp/ En64-Bit ModeCompat/Leg ModeDescription90+rwXCHG AX, r16OValidValidExchange r16 with AX.90+rwXCHG r16, AXOValid ValidExchange AX with r16.90+rdXCHG EAX, r32OValid ValidExchange r32 with EAX.REX.W + 90+rdXCHG RAX, r64OValidN.E.Exchange r64 with RAX.90+rdXCHG r32, EAXOValid ValidExchange EAX with r32.REX.W + 90+rdXCHG r64, RAXOValidN.E.Exchange RAX with r64.86 /rXCHG r/m8, r8MRValid ValidExchange r8 (byte register) with byte from r/m8.REX + 86 /rXCHG r/m8*, r8*MRValidN.E.Exchange r8 (byte register) with byte from r/m8.86 /rXCHG r8, r/m8RMValid ValidExchange byte from r/m8 with r8 (byte register).REX + 86 /rXCHG r8*, r/m8*RMValidN.E.Exchange byte from r/m8 with r8 (byte register).87 /rXCHG r/m16, r16MRValidValidExchange r16 with word from r/m16.87 /rXCHG r16, r/m16RMValid ValidExchange word from r/m16 with r16.87 /rXCHG r/m32, r32MRValid ValidExchange r32 with doubleword from r/m32.REX.W + 87 /rXCHG r/m64, r64MRValidN.E.Exchange r64 with quadword from r/m64.87 /rXCHG r32, r/m32RMValid ValidExchange doubleword from r/m32 with r32.REX.W + 87 /rXCHG r64, r/m64RMValid N.E.Exchange quadword from r/m64 with r64.NOTES:*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. Op/EnOperand 1Operand 2Operand 3Operand 4OAX/EAX/RAX (r, w)opcode + rd (r, w)NANAOopcode + rd (r, w)AX/EAX/RAX (r, w)NANAMRModRM:r/m (r, w)ModRM:reg (r)NANARMModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlNOTEXCHG (E)AX, (E)AX (encoded instruction byte is 90H) is an alias for NOP regardless of data size prefixes, including REX.W.OperationTEMP := DEST;DEST := SRC;SRC := TEMP;Flags AffectedNone.Protected Mode Exceptions#GP(0)If either operand is in a non-writable segment.If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used but the destination is not a memory operand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SS segment limit.#UD If the LOCK prefix is used but the destination is not a memory operand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SS segment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made.#UD If the LOCK prefix is used but the destination is not a memory operand.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.#UD If the LOCK prefix is used but the destination is not a memory operand.

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