image/svg+xmlXBEGIN — Transactional BeginInstruction Operand EncodingDescriptionThe XBEGIN instruction specifies the start of an RTM code region. If the logical processor was not already in trans-actional execution, then the XBEGIN instruction causes the logical processor to transition into transactional execu-tion. The XBEGIN instruction that transitions the logical processor into transactional execution is referred to as the outermost XBEGIN instruction. The instruction also specifies a relative offset to compute the address of the fallback code path following a transactional abort. (Use of the 16-bit operand size does not cause this address to be trun-cated to 16 bits, unlike a near jump to a relative offset.)On an RTM abort, the logical processor discards all architectural register and memory updates performed during the RTM execution and restores architectural state to that corresponding to the outermost XBEGIN instruction. The fallback address following an abort is computed from the outermost XBEGIN instruction. OperationXBEGINIF RTM_NEST_COUNT < MAX_RTM_NEST_COUNTTHENRTM_NEST_COUNT++IF RTM_NEST_COUNT = 1 THENIF 64-bit ModeTHENIF OperandSize = 16THEN fallbackRIP := RIP + SignExtend64(rel16);ELSE fallbackRIP := RIP + SignExtend64(rel32);FI;IF fallbackRIP is not canonicalTHEN #GP(0);FI;ELSEIF OperandSize = 16THEN fallbackEIP := EIP + SignExtend32(rel16);ELSE fallbackEIP := EIP + rel32;FI;IF fallbackEIP outside code segment limitTHEN #GP(0);FI;FI;RTM_ACTIVE := 1Enter RTM Execution (* record register state, start tracking memory state*)Opcode/InstructionOp/ En64/32bit Mode SupportCPUID Feature FlagDescriptionC7 F8XBEGIN rel16AV/VRTMSpecifies the start of an RTM region. Provides a 16-bit relative offset to compute the address of the fallback instruction address at which execution resumes following an RTM abort.C7 F8XBEGIN rel32AV/VRTMSpecifies the start of an RTM region. Provides a 32-bit relative offset to compute the address of the fallback instruction address at which execution resumes following an RTM abort.Op/EnOperand 1Operand2Operand3Operand4AOffsetNANANA

image/svg+xmlFI; (* RTM_NEST_COUNT = 1 *)ELSE (* RTM_NEST_COUNT = MAX_RTM_NEST_COUNT *)GOTO RTM_ABORT_PROCESSINGFI;(* For any RTM abort condition encountered during RTM execution *)RTM_ABORT_PROCESSING:Restore architectural register stateDiscard memory updates performed in transactionUpdate EAX with statusRTM_NEST_COUNT := 0RTM_ACTIVE := 0IF 64-bit modeTHENRIP := fallbackRIPELSEEIP := fallbackEIPFI;ENDFlags AffectedNoneIntel C/C++ Compiler Intrinsic EquivalentXBEGIN:unsigned int _xbegin( void );SIMD Floating-Point ExceptionsNoneProtected Mode Exceptions#UDCPUID.(EAX=7, ECX=0):EBX.RTM[bit 11]=0.If LOCK prefix is used.#GP(0)If the fallback address is outside the CS segment.Real-Address Mode Exceptions#GP(0)If the fallback address is outside the address space 0000H and FFFFH.#UDCPUID.(EAX=7, ECX=0):EBX.RTM[bit 11]=0.If LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If the fallback address is outside the address space 0000H and FFFFH.#UDCPUID.(EAX=7, ECX=0):EBX.RTM[bit 11]=0.If LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.

image/svg+xml64-bit Mode Exceptions#UDCPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0.If LOCK prefix is used.#GP(0)If the fallback address is non-canonical.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.