image/svg+xml XABORT — Transactional Abort Instruction Operand Encoding Description XABORT forces an RTM abort. Following an RTM abort, the logical processor resumes execution at the fallback address computed through the outermost XBEGIN instruction. The EAX register is updated to reflect an XABORT instruction caused the abort, and the imm8 argument will be provided in bits 31:24 of EAX. Operation XABORT IF RTM_ACTIVE = 0 THEN Treat as NOP; ELSE GOTO RTM_ABORT_PROCESSING; FI; (* For any RTM abort condition encountered during RTM execution *) RTM_ABORT_PROCESSING: Restore architectural register state; Discard memory updates performed in transaction; Update EAX with status and XABORT argument; RTM_NEST_COUNT:= 0; RTM_ACTIVE:= 0; IF 64-bit Mode THEN RIP:= fallbackRIP; ELSE EIP := fallbackEIP; FI; END Flags Affected None Intel C/C++ Compiler Intrinsic Equivalent XABORT:void _xabort( unsigned int); SIMD Floating-Point Exceptions None Opcode/InstructionOp/ En 64/32bit Mode Support CPUID Feature Flag Description C6 F8 ib XABORT imm8 AV/VRTMCauses an RTM abort if in RTM execution Op/EnOperand 1Operand2Operand3Operand4 Aimm8NANANA image/svg+xml Other Exceptions #UDCPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0. If LOCK prefix is used. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .