VTESTPD/VTESTPS—Packed Bit TestInstruction Operand EncodingDescriptionVTESTPS performs a bitwise comparison of all the sign bits of the packed single-precision elements in the first source operation and corresponding sign bits in the second source operand. If the AND of the source sign bits with the dest sign bits produces all zeros, the ZF is set else the ZF is clear. If the AND of the source sign bits with the inverted dest sign bits produces all zeros the CF is set else the CF is clear. An attempt to execute VTESTPS with VEX.W=1 will cause #UD.VTESTPD performs a bitwise comparison of all the sign bits of the double-precision elements in the first source operation and corresponding sign bits in the second source operand. If the AND of the source sign bits with the dest sign bits produces all zeros, the ZF is set else the ZF is clear. If the AND the source sign bits with the inverted dest sign bits produces all zeros the CF is set else the CF is clear. An attempt to execute VTESTPS with VEX.W=1 will cause #UD.The first source register is specified by the ModR/M reg field.128-bit version: The first source register is an XMM register. The second source register can be an XMM register or a 128-bit memory location. The destination register is not modified.VEX.256 encoded version: The first source register is a YMM register. The second source register can be a YMM register or a 256-bit memory location. The destination register is not modified.Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.Opcode/InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescriptionVEX.128.66.0F38.W0 0E /rVTESTPS xmm1, xmm2/m128RMV/VAVXSet ZF and CF depending on sign bit AND and ANDN of packed single-precision floating-point sources.VEX.256.66.0F38.W0 0E /rVTESTPS ymm1, ymm2/m256RMV/VAVXSet ZF and CF depending on sign bit AND and ANDN of packed single-precision floating-point sources.VEX.128.66.0F38.W0 0F /rVTESTPD xmm1, xmm2/m128RMV/VAVXSet ZF and CF depending on sign bit AND and ANDN of packed double-precision floating-point sources.VEX.256.66.0F38.W0 0F /rVTESTPD ymm1, ymm2/m256RMV/VAVXSet ZF and CF depending on sign bit AND and ANDN of packed double-precision floating-point sources.Op/EnOperand 1Operand 2Operand 3Operand 4RMModRM:reg (r)ModRM:r/m (r)NANA
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