VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Packed Single, Packed Double with Signed Dword and Qword IndicesInstruction Operand EncodingDescriptionStores up to 16 elements (or 8 elements) in doubleword/quadword vector zmm1 to the memory locations pointed by base address BASE_ADDR and index vector VINDEX, with scale SCALE. The elements are specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only be stored if their corre-sponding mask bit is one. The entire mask register will be set to zero by this instruction unless it triggers an excep-tion.This instruction can be suspended by an exception if at least one element is already scattered (i.e., if the exception is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination register and the mask register (k1) are partially updated. If any traps or interrupts are pending from already scat-tered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction breakpoint is not re-triggered when the instruction is continued.Note that:•Only writes to overlapping vector indices are guaranteed to be ordered with respect to each other (from LSB to MSB of the source registers). Note that this also include partially overlapping vector indices. Writes that are not overlapped may happen in any order. Memory ordering with other instructions follows the Intel-64 memory ordering model. Note that this does not account for non-overlapping indices that map into the same physical address locations.Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.128.66.0F38.W0 A2 /vsib VSCATTERDPS vm32x {k1}, xmm1AV/VAVX512VLAVX512FUsing signed dword indices, scatter single-precision floating-point values to memory using writemask k1.EVEX.256.66.0F38.W0 A2 /vsib VSCATTERDPS vm32y {k1}, ymm1AV/VAVX512VLAVX512FUsing signed dword indices, scatter single-precision floating-point values to memory using writemask k1.EVEX.512.66.0F38.W0 A2 /vsib VSCATTERDPS vm32z {k1}, zmm1AV/VAVX512FUsing signed dword indices, scatter single-precision floating-point values to memory using writemask k1.EVEX.128.66.0F38.W1 A2 /vsibVSCATTERDPD vm32x {k1}, xmm1AV/VAVX512VLAVX512FUsing signed dword indices, scatter double-precision floating-point values to memory using writemask k1.EVEX.256.66.0F38.W1 A2 /vsib VSCATTERDPD vm32x {k1}, ymm1AV/VAVX512VLAVX512FUsing signed dword indices, scatter double-precision floating-point values to memory using writemask k1.EVEX.512.66.0F38.W1 A2 /vsib VSCATTERDPD vm32y {k1}, zmm1AV/VAVX512FUsing signed dword indices, scatter double-precision floating-point values to memory using writemask k1.EVEX.128.66.0F38.W0 A3 /vsibVSCATTERQPS vm64x {k1}, xmm1AV/VAVX512VLAVX512FUsing signed qword indices, scatter single-precision floating-point values to memory using writemask k1.EVEX.256.66.0F38.W0 A3 /vsib VSCATTERQPS vm64y {k1}, xmm1AV/VAVX512VLAVX512FUsing signed qword indices, scatter single-precision floating-point values to memory using writemask k1.EVEX.512.66.0F38.W0 A3 /vsib VSCATTERQPS vm64z {k1}, ymm1AV/VAVX512FUsing signed qword indices, scatter single-precision floating-point values to memory using writemask k1.EVEX.128.66.0F38.W1 A3 /vsib VSCATTERQPD vm64x {k1}, xmm1AV/VAVX512VLAVX512FUsing signed qword indices, scatter double-precision floating-point values to memory using writemask k1.EVEX.256.66.0F38.W1 A3 /vsib VSCATTERQPD vm64y {k1}, ymm1AV/VAVX512VLAVX512FUsing signed qword indices, scatter double-precision floating-point values to memory using writemask k1.EVEX.512.66.0F38.W1 A3 /vsib VSCATTERQPD vm64z {k1}, zmm1AV/VAVX512FUsing signed qword indices, scatter double-precision floating-point values to memory using writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ATuple1 ScalarBaseReg (R): VSIB:base,VectorReg(R): VSIB:indexModRM:reg (r)NANA
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