image/svg+xmlVSCALEFSS—Scale Scalar Float32 Value With Float32 ValueInstruction Operand EncodingDescriptionPerforms a floating-point scale of the scalar single-precision floating-point value in the first source operand by multiplying it by 2 power of the float32 value in second source operand.The equation of this operation is given by:xmm1 := xmm2*2floor(xmm3).Floor(xmm3) means maximum integer value ≤ xmm3.If the result cannot be represented in single precision, then the proper overflow response (for positive scaling operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in MXCSR (exception mask bits, FTZ bit), and on the SAE bit.EVEX encoded version: The first source operand is an XMM register. The second source operand is an XMM register or a memory location. The destination operand is an XMM register conditionally updated with writemask k1.Handling of special-case input values are listed in Table 5-21 and Table 5-23.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.LLIG.66.0F38.W0 2D /r VSCALEFSS xmm1 {k1}{z}, xmm2, xmm3/m32{er}AV/VAVX512FScale the scalar single-precision floating-point value in xmm2 using floating-point value from xmm3/m32. Under writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ATuple1 ScalarModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlOperationSCALE(SRC1, SRC2){; Check for denormal operandsTMP_SRC2 := SRC2TMP_SRC1 := SRC1IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0/* SRC2 is a 32 bits floating-point value */DEST[31:0] := TMP_SRC1[31:0] * POW(2, Floor(TMP_SRC2[31:0]))}VSCALEFSS (EVEX encoded version)IF (EVEX.b= 1) and SRC2 *is a register*THENSET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);FI;IF k1[0] OR *no writemask*THEN DEST[31:0] := SCALE(SRC1[31:0], SRC2[31:0])ELSE IF *merging-masking*; merging-maskingTHEN *DEST[31:0] remains unchanged*ELSE ; zeroing-maskingDEST[31:0] := 0FIFI;DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0Intel C/C++ Compiler Intrinsic EquivalentVSCALEFSS __m128 _mm_scalef_round_ss(__m128 a, __m128 b, int);VSCALEFSS __m128 _mm_mask_scalef_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);VSCALEFSS __m128 _mm_maskz_scalef_round_ss(__mmask8 k, __m128 a, __m128 b, int);SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, Denormal (for Src1).Denormal is not reported for Src2.Other ExceptionsSee Table2-47, “Type E3 Class Exception Conditions”.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.