image/svg+xmlVRSQRT28PD—Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative ErrorInstruction Operand EncodingDescriptionComputes the reciprocal square root of the float64 values in the source operand (the second operand) and store the results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than 2^-28 of maximum relative error. If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero) source numbers, as well as -∞, return the canonical NaN and set the Invalid Flag (#I).A value of -0 must return -∞ and set the DivByZero flags (#Z). Negative numbers should return NaN and set the Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative denormals return -∞ and set the DivByZero flag.The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1. EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.OperationVRSQRT28PD (EVEX encoded versions) (KL, VL) = (8, 512)FOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask* THENIF (EVEX.b = 1) AND (SRC *is memory*)THEN DEST[i+63:i] := (1.0/ SQRT(SRC[63:0]));ELSE DEST[i+63:i] := (1.0/ SQRT(SRC[i+63:i]));FI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+63:i] := 0FI;FI;ENDFOR;Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.512.66.0F38.W1 CC /rVRSQRT28PD zmm1 {k1}{z}, zmm2/m512/m64bcst {sae}AV/VAVX512ERComputes approximations to the Reciprocal square root (<2^-28 relative error) of the packed double-precision floating-point values from zmm2/m512/m64bcst and stores result in zmm1with writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4AFullModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentVRSQRT28PD __m512d _mm512_rsqrt28_round_pd(__m512d a, int sae);VRSQRT28PD __m512d _mm512_mask_rsqrt28_round_pd(__m512d s, __mmask8 m,__m512d a, int sae);VRSQRT28PD __m512d _mm512_maskz_rsqrt28_round_pd(__mmask8 m,__m512d a, int sae);SIMD Floating-Point ExceptionsInvalid (if SNaN input), Divide-by-zeroOther ExceptionsSee Table2-46, “Type E2 Class Exception Conditions”.Table 6-7. VRSQRT28PD Special CasesInput valueResult valueCommentsNANQNAN(input)If (SRC = SNaN) then #IX = 2-2n2nX < 0QNaN_IndefiniteIncluding -INFX = -0 or negative denormal-INF#ZX = +0 or positive denormal+INF#ZX = +INF+0

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