image/svg+xml VREDUCESD—Perform a Reduction Transformation on a Scalar Float64 Value Instruction Operand EncodingDescriptionPerform a reduction transformation of the binary encoded double-precision FP value in the low qword element of the second source operand (the third operand) and store the reduced result in binary FP format to the low qword element of the destination operand (the first operand) under the writemask k1. Bits 127:64 of the destination operand are copied from respective qword elements of the first source operand (the second operand). The reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source value, where M is a unsigned integer specified by imm8[7:4], see Figure5-28. Specifically, the reduction transfor-mation can be expressed as:dest = src – (ROUND(2M*src))*2-M;where “Round()” treats “src”, “2M”, and their product as binary FP numbers with normalized significand and bi-ased exponents.The magnitude of the reduced result can be expressed by considering src= 2p*man2,where ‘man2’ is the normalized significand and ‘p’ is the unbiased exponent Then if RC = RNE: 0<=|Reduced Result|<=2p-M-1Then if RC ≠ RNE: 0<=|Reduced Result|<2p-MThis instruction might end up with a precision exception set. However, in case of SPE set (i.e. Suppress Precision Exception, which is imm8[3]=1), no precision exception is reported.The operation is write masked.Handling of special case of input values are listed in Table 5-15.OperationReduceArgumentDP(SRC[63:0], imm8[7:0]){// Check for NaNIF (SRC [63:0] = NAN) THENRETURN (Convert SRC[63:0] to QNaN); FI;M := imm8[7:4]; // Number of fraction bits of the normalized significand to be subtractedRC := imm8[1:0];// Round Control for ROUND() operationRC source := imm[2];SPE := imm[3];// Suppress Precision ExceptionTMP[63:0] := 2-M *{ROUND(2M*SRC[63:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2M as standard binary FP valuesTMP[63:0] := SRC[63:0] – TMP[63:0]; // subtraction under the same RC,SPE controlsRETURN TMP[63:0]; // binary encoded FP with biased exponent and normalized significand}Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.LLIG.66.0F3A.W1 57VREDUCESD xmm1 {k1}{z}, xmm2, xmm3/m64{sae}, imm8/r AV/VAVX512DQPerform a reduction transformation on a scalar double-precision floating point value in xmm3/m64 by subtracting a number of fraction bits specified by the imm8 field. Also, upper double precision floating-point value (bits[127:64]) from xmm2 are copied to xmm1[127:64]. Stores the result in xmm1 register.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ATuple1 ScalarModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlVREDUCESD IF k1[0] or *no writemask*THENDEST[63:0] := ReduceArgumentDP(SRC2[63:0], imm8[7:0])ELSE IF *merging-masking*; merging-maskingTHEN *DEST[63:0] remains unchanged*ELSE ; zeroing-maskingTHEN DEST[63:0] = 0FI;FI;DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0Intel C/C++ Compiler Intrinsic EquivalentVREDUCESD __m128d _mm_mask_reduce_sd( __m128d a, __m128d b, int imm, int sae)VREDUCESD __m128d _mm_mask_reduce_sd(__m128d s, __mmask16 k, __m128d a, __m128d b, int imm, int sae)VREDUCESD __m128d _mm_maskz_reduce_sd(__mmask16 k, __m128d a, __m128d b, int imm, int sae)SIMD Floating-Point ExceptionsInvalid, PrecisionIf SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).Other ExceptionsSee Table2-47, “Type E3 Class Exception Conditions”.

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