image/svg+xmlVREDUCEPD—Perform Reduction Transformation on Packed Float64 ValuesInstruction Operand EncodingDescriptionPerform reduction transformation of the packed binary encoded double-precision FP values in the source operand (the second operand) and store the reduced results in binary FP format to the destination operand (the first operand) under the writemask k1. The reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source value, where M is a unsigned integer specified by imm8[7:4], see Figure5-28. Specifically, the reduction transfor-mation can be expressed as:dest = src – (ROUND(2M*src))*2-M;where “Round()” treats “src”, “2M”, and their product as binary FP numbers with normalized significand and bi-ased exponents.The magnitude of the reduced result can be expressed by considering src= 2p*man2,where ‘man2’ is the normalized significand and ‘p’ is the unbiased exponent Then if RC = RNE: 0<=|Reduced Result|<=2p-M-1Then if RC ≠ RNE: 0<=|Reduced Result|<2p-MThis instruction might end up with a precision exception set. However, in case of SPE set (i.e. Suppress Precision Exception, which is imm8[3]=1), no precision exception is reported.EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.128.66.0F3A.W1 56 /r ibVREDUCEPD xmm1 {k1}{z}, xmm2/m128/m64bcst, imm8AV/VAVX512VLAVX512DQPerform reduction transformation on packed double-precision floating point values in xmm2/m128/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in xmm1 register under writemask k1.EVEX.256.66.0F3A.W1 56 /r ibVREDUCEPD ymm1 {k1}{z}, ymm2/m256/m64bcst, imm8AV/VAVX512VLAVX512DQPerform reduction transformation on packed double-precision floating point values in ymm2/m256/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in ymm1 register under writemask k1.EVEX.512.66.0F3A.W1 56 /r ibVREDUCEPD zmm1 {k1}{z}, zmm2/m512/m64bcst{sae}, imm8AV/VAVX512DQPerform reduction transformation on double-precision floating point values in zmm2/m512/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in zmm1 register under writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4AFullModRM:reg (w)ModRM:r/m (r)Imm8NAFigure 5-28. Imm8 Controls for VREDUCEPD/SD/PS/SS70246531Round Control OverrideFixed point lengthImm8[7:4] : Number of fixed points to subtractRSImm8[1:0] = 00b : Round nearest evenImm8[1:0] = 01b : Round downImm8[1:0] = 10b : Round upImm8[1:0] = 11b : Truncateimm8SPERound Select: Imm8[2] Imm8[2] = 0b : Use Imm8[1:0]Imm8[2] = 1b : Use MXCSRSuppress Precision Exception: Imm8[3] Imm8[3] = 0b : Use MXCSR exception maskImm8[3] = 1b : Suppress

image/svg+xmlHandling of special case of input values are listed in Table 5-15.* Round control = (imm8.MS1)? MXCSR.RC: imm8.RCOperationReduceArgumentDP(SRC[63:0], imm8[7:0]){// Check for NaNIF (SRC [63:0] = NAN) THENRETURN (Convert SRC[63:0] to QNaN); FI;M := imm8[7:4]; // Number of fraction bits of the normalized significand to be subtractedRC := imm8[1:0];// Round Control for ROUND() operationRC source := imm[2];SPE := imm[3];// Suppress Precision ExceptionTMP[63:0] := 2-M *{ROUND(2M*SRC[63:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2M as standard binary FP valuesTMP[63:0] := SRC[63:0] – TMP[63:0]; // subtraction under the same RC,SPE controlsRETURN TMP[63:0]; // binary encoded FP with biased exponent and normalized significand}VREDUCEPD (KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask* THENIF (EVEX.b == 1) AND (SRC *is memory*)THEN DEST[i+63:i] := ReduceArgumentDP(SRC[63:0], imm8[7:0]);ELSE DEST[i+63:i] := ReduceArgumentDP(SRC[i+63:i], imm8[7:0]);FI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+63:i] = 0FI;FI;ENDFOR;DEST[MAXVL-1:VL] := 0Table 5-15. VREDUCEPD/SD/PS/SS Special CasesRound ModeReturned value |Src1| < 2-M-1RNESrc1|Src1| < 2-MRPI, Src1 > 0Round (Src1-2-M) *RPI, Src1 ≤ 0Src1RNI, Src1 ≥ 0Src1RNI, Src1 < 0Round (Src1+2-M) *Src1 = ±0, orDest = ±0 (Src1!=INF)NOT RNI+0.0RNI-0.0Src1 = ±INFany+0.0Src1= ±NANn/aQNaN(Src1)

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentVREDUCEPD __m512d _mm512_mask_reduce_pd( __m512d a, int imm, int sae)VREDUCEPD __m512d _mm512_mask_reduce_pd(__m512d s, __mmask8 k, __m512d a, int imm, int sae)VREDUCEPD __m512d _mm512_maskz_reduce_pd(__mmask8 k, __m512d a, int imm, int sae)VREDUCEPD __m256d _mm256_mask_reduce_pd( __m256d a, int imm)VREDUCEPD __m256d _mm256_mask_reduce_pd(__m256d s, __mmask8 k, __m256d a, int imm)VREDUCEPD __m256d _mm256_maskz_reduce_pd(__mmask8 k, __m256d a, int imm)VREDUCEPD __m128d _mm_mask_reduce_pd( __m128d a, int imm)VREDUCEPD __m128d _mm_mask_reduce_pd(__m128d s, __mmask8 k, __m128d a, int imm)VREDUCEPD __m128d _mm_maskz_reduce_pd(__mmask8 k, __m128d a, int imm)SIMD Floating-Point ExceptionsInvalid, PrecisionIf SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).Other ExceptionsSee Table2-46, “Type E2 Class Exception Conditions”; additionally:#UD If EVEX.vvvv != 1111B.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.