image/svg+xml VRCP28PD—Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error Instruction Operand Encoding Description Computes the reciprocal approximation of the float64 values in the source operand (the second operand) and store the results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than 2^-28 of maximum relative error. Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results are flushed to zeros and do not signal #UE, irrespective of MXCSR.FTZ. If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is ± ∞ , ±0.0 is returned for that element. Also, if any source element is ±0.0, ± ∞ is returned for that element. The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1. EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer- ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2 . Operation VRCP28PD (EVEX encoded versions) (KL, VL) = (8, 512) FOR j := 0 TO KL-1 i := j * 64 IF k1[j] OR *no writemask* THEN IF (EVEX.b = 1) AND (SRC *is memory*) THEN DEST[i+63:i] := RCP_28_DP(1.0/SRC[63:0]); ELSE DEST[i+63:i] := RCP_28_DP(1.0/SRC[i+63:i]); FI; ELSE IF *merging-masking*; merging-masking THEN *DEST[i+63:i] remains unchanged* ELSE ; zeroing-masking DEST[i+63:i] := 0 FI; FI; ENDFOR; Opcode/ Instruction Op / En 64/32 bit Mode Support CPUID Feature Flag Description EVEX.512.66.0F38.W1 CA /r VRCP28PD zmm1 {k1}{z}, zmm2/m512/m64bcst {sae} AV/VAVX512ERComputes the approximate reciprocals ( < 2^-28 relative error) of the packed double-precision floating-point values in zmm2/m512/m64bcst and stores the results in zmm1. Under writemask. Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4 AFullModRM:reg (w)ModRM:r/m (r)NANA image/svg+xml Intel C/C++ Compiler Intrinsic Equivalent VRCP28PD __m512d _mm512_rcp28_round_pd ( __m512d a, int sae); VRCP28PD __m512d _mm512_mask_rcp28_round_pd(__m512d a, __mmask8 m, __m512d b, int sae); VRCP28PD __m512d _mm512_maskz_rcp28_round_pd( __mmask8 m, __m512d b, int sae); SIMD Floating-Point Exceptions Invalid (if SNaN input), Divide-by-zero Other Exceptions See Table2-46, “Type E2 Class Exception Conditions”. Table 6-3. VRCP28PD Special Cases Input valueResult valueComments NANQNAN(input)If (SRC = SNaN) then #I 0 ≤ X < 2 -1022 INFPositive input denormal or zero; #Z -2 -1022 < X ≤ -0-INFNegative input denormal or zero; #Z X > 2 1022 +0.0f X < -2 1022 -0.0f X = + ∞ +0.0f X = - ∞ -0.0f X = 2 -n 2 n Exact result (unless input/output is a denormal) X = -2 -n -2 n Exact result (unless input/output is a denormal) This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .