VPTESTNMB/W/D/Q—Logical NAND and SetOpcode/InstructionOp/En64/32 bit Mode SupportCPUIDDescriptionEVEX.128.F3.0F38.W0 26 /rVPTESTNMB k2 {k1}, xmm2, xmm3/m128AV/V AVX512VLAVX512BWBitwise NAND of packed byte integers in xmm2 and xmm3/m128 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1.EVEX.256.F3.0F38.W0 26 /rVPTESTNMB k2 {k1}, ymm2, ymm3/m256AV/V AVX512VLAVX512BWBitwise NAND of packed byte integers in ymm2 and ymm3/m256 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1.EVEX.512.F3.0F38.W0 26 /rVPTESTNMB k2 {k1}, zmm2, zmm3/m512AV/V AVX512FAVX512BWBitwise NAND of packed byte integers in zmm2 and zmm3/m512 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1.EVEX.128.F3.0F38.W1 26 /rVPTESTNMW k2 {k1}, xmm2, xmm3/m128AV/V AVX512VLAVX512BWBitwise NAND of packed word integers in xmm2 and xmm3/m128 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1.EVEX.256.F3.0F38.W1 26 /rVPTESTNMW k2 {k1}, ymm2, ymm3/m256AV/V AVX512VLAVX512BWBitwise NAND of packed word integers in ymm2 and ymm3/m256 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1.EVEX.512.F3.0F38.W1 26 /rVPTESTNMW k2 {k1}, zmm2, zmm3/m512AV/V AVX512FAVX512BWBitwise NAND of packed word integers in zmm2 and zmm3/m512 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1.EVEX.128.F3.0F38.W0 27 /rVPTESTNMD k2 {k1}, xmm2, xmm3/m128/m32bcstBV/V AVX512VLAVX512FBitwise NAND of packed doubleword integers in xmm2 and xmm3/m128/m32bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1.EVEX.256.F3.0F38.W0 27 /rVPTESTNMD k2 {k1}, ymm2, ymm3/m256/m32bcstBV/V AVX512VLAVX512FBitwise NAND of packed doubleword integers in ymm2 and ymm3/m256/m32bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1.EVEX.512.F3.0F38.W0 27 /rVPTESTNMD k2 {k1}, zmm2, zmm3/m512/m32bcstBV/V AVX512FBitwise NAND of packed doubleword integers in zmm2 and zmm3/m512/m32bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1.EVEX.128.F3.0F38.W1 27 /rVPTESTNMQ k2 {k1}, xmm2, xmm3/m128/m64bcstBV/V AVX512VLAVX512FBitwise NAND of packed quadword integers in xmm2 and xmm3/m128/m64bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1.EVEX.256.F3.0F38.W1 27 /rVPTESTNMQ k2 {k1}, ymm2, ymm3/m256/m64bcstBV/V AVX512VLAVX512FBitwise NAND of packed quadword integers in ymm2 and ymm3/m256/m64bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1.EVEX.512.F3.0F38.W1 27 /rVPTESTNMQ k2 {k1}, zmm2, zmm3/m512/m64bcstBV/V AVX512FBitwise NAND of packed quadword integers in zmm2 and zmm3/m512/m64bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1.
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