image/svg+xmlVPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic Instruction Operand EncodingOpcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionVEX.128.66.0F38.W0 46 /rVPSRAVD xmm1, xmm2, xmm3/m128AV/VAVX2Shift doublewords in xmm2 right by amount specified in the corresponding element of xmm3/m128 while shifting in sign bits.VEX.256.66.0F38.W0 46 /rVPSRAVD ymm1, ymm2, ymm3/m256AV/VAVX2Shift doublewords in ymm2 right by amount specified in the corresponding element of ymm3/m256 while shifting in sign bits.EVEX.128.66.0F38.W1 11 /rVPSRAVW xmm1 {k1}{z}, xmm2, xmm3/m128BV/VAVX512VLAVX512BWShift words in xmm2 right by amount specified in the corresponding element of xmm3/m128 while shifting in sign bits using writemask k1.EVEX.256.66.0F38.W1 11 /rVPSRAVW ymm1 {k1}{z}, ymm2, ymm3/m256BV/VAVX512VLAVX512BWShift words in ymm2 right by amount specified in the corresponding element of ymm3/m256 while shifting in sign bits using writemask k1.EVEX.512.66.0F38.W1 11 /rVPSRAVW zmm1 {k1}{z}, zmm2, zmm3/m512BV/VAVX512BWShift words in zmm2 right by amount specified in the corresponding element of zmm3/m512 while shifting in sign bits using writemask k1.EVEX.128.66.0F38.W0 46 /rVPSRAVD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcstCV/VAVX512VLAVX512FShift doublewords in xmm2 right by amount specified in the corresponding element of xmm3/m128/m32bcst while shifting in sign bits using writemask k1.EVEX.256.66.0F38.W0 46 /rVPSRAVD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcstCV/VAVX512VLAVX512FShift doublewords in ymm2 right by amount specified in the corresponding element of ymm3/m256/m32bcst while shifting in sign bits using writemask k1.EVEX.512.66.0F38.W0 46 /rVPSRAVD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcstCV/VAVX512FShift doublewords in zmm2 right by amount specified in the corresponding element of zmm3/m512/m32bcst while shifting in sign bits using writemask k1.EVEX.128.66.0F38.W1 46 /rVPSRAVQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstCV/VAVX512VLAVX512FShift quadwords in xmm2 right by amount specified in the corresponding element of xmm3/m128/m64bcst while shifting in sign bits using writemask k1.EVEX.256.66.0F38.W1 46 /rVPSRAVQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstCV/VAVX512VLAVX512FShift quadwords in ymm2 right by amount specified in the corresponding element of ymm3/m256/m64bcst while shifting in sign bits using writemask k1.EVEX.512.66.0F38.W1 46 /rVPSRAVQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstCV/VAVX512FShift quadwords in zmm2 right by amount specified in the corresponding element of zmm3/m512/m64bcst while shifting in sign bits using writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NABFull MemModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NACFullModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlDescriptionShifts the bits in the individual data elements (word/doublewords/quadword) in the first source operand (the second operand) to the right by the number of bits specified in the count value of respective data elements in the second source operand (the third operand). As the bits in the data elements are shifted right, the empty high-order bits are set to the MSB (sign extension). The count values are specified individually in each data element of the second source operand. If the unsigned integer value specified in the respective data element of the second source operand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination data element is filled with the corresponding sign bit of the source element.VEX.128 encoded version: The destination and first source operands are XMM registers. The count operand can be either an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding destination register are zeroed.VEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be either an YMM register or a 256-bit memory. Bits (MAXVL-1:256) of the corresponding destination register are zeroed.EVEX.512/256/128 encoded VPSRAVD/W: The destination and first source operands are ZMM/YMM/XMM registers. The count operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination is conditionally updated with writemask k1.EVEX.512/256/128 encoded VPSRAVQ: The destination and first source operands are ZMM/YMM/XMM registers. The count operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is conditionally updated with writemask k1.OperationVPSRAVW (EVEX encoded version) (KL, VL) = (8, 128), (16, 256), (32, 512)FOR j := 0 TO KL-1i := j * 16IF k1[j] OR *no writemask*THEN COUNT := SRC2[i+3:i]IF COUNT < 16THEN DEST[i+15:i] := SignExtend(SRC1[i+15:i] >> COUNT)ELSE FOR k := 0 TO 15 DEST[i+k] := SRC1[i+15]ENDFOR;FIELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+15:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+15:i] := 0FIFI;ENDFOR;DEST[MAXVL-1:VL] := 0;

image/svg+xmlVPSRAVD (VEX.128 version)COUNT_0 := SRC2[31 : 0](* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)COUNT_3 := SRC2[127 : 96];DEST[31:0] := SignExtend(SRC1[31:0] >> COUNT_0);(* Repeat shift operation for 2nd through 4th dwords *)DEST[127:96] := SignExtend(SRC1[127:96] >> COUNT_3);DEST[MAXVL-1:128] := 0;VPSRAVD (VEX.256 version)COUNT_0 := SRC2[31 : 0];(* Repeat Each COUNT_i for the 2nd through 8th dwords of SRC2*)COUNT_7 := SRC2[255 : 224];DEST[31:0] := SignExtend(SRC1[31:0] >> COUNT_0);(* Repeat shift operation for 2nd through 7th dwords *)DEST[255:224] := SignExtend(SRC1[255:224] >> COUNT_7);DEST[MAXVL-1:256] := 0;VPSRAVD (EVEX encoded version) (KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask* THENIF (EVEX.b = 1) AND (SRC2 *is memory*)THEN COUNT := SRC2[4:0]IF COUNT < 32THEN DEST[i+31:i] := SignExtend(SRC1[i+31:i] >> COUNT)ELSE FOR k := 0 TO 31 DEST[i+k] := SRC1[i+31]ENDFOR;FIELSE COUNT := SRC2[i+4:i]IF COUNT < 32THEN DEST[i+31:i] := SignExtend(SRC1[i+31:i] >> COUNT)ELSE FOR k := 0 TO 31 DEST[i+k] := SRC1[i+31]ENDFOR;FIFI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[31:0] remains unchanged*ELSE ; zeroing-maskingDEST[31:0] := 0FIFI;ENDFOR;DEST[MAXVL-1:VL] := 0;

image/svg+xmlVPSRAVQ (EVEX encoded version) (KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask* THENIF (EVEX.b = 1) AND (SRC2 *is memory*)THEN COUNT := SRC2[5:0]IF COUNT < 64THEN DEST[i+63:i] := SignExtend(SRC1[i+63:i] >> COUNT)ELSE FOR k := 0 TO 63 DEST[i+k] := SRC1[i+63]ENDFOR;FIELSE COUNT := SRC2[i+5:i]IF COUNT < 64THEN DEST[i+63:i] := SignExtend(SRC1[i+63:i] >> COUNT)ELSE FOR k := 0 TO 63 DEST[i+k] := SRC1[i+63]ENDFOR;FIFI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[63:0] remains unchanged*ELSE ; zeroing-maskingDEST[63:0] := 0FIFI;ENDFOR;DEST[MAXVL-1:VL] := 0;

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentVPSRAVD __m512i _mm512_srav_epi32(__m512i a, __m512i cnt);VPSRAVD __m512i _mm512_mask_srav_epi32(__m512i s, __mmask16 m, __m512i a, __m512i cnt);VPSRAVD __m512i _mm512_maskz_srav_epi32(__mmask16 m, __m512i a, __m512i cnt);VPSRAVD __m256i _mm256_srav_epi32(__m256i a, __m256i cnt);VPSRAVD __m256i _mm256_mask_srav_epi32(__m256i s, __mmask8 m, __m256i a, __m256i cnt);VPSRAVD __m256i _mm256_maskz_srav_epi32(__mmask8 m, __m256i a, __m256i cnt);VPSRAVD __m128i _mm_srav_epi32(__m128i a, __m128i cnt);VPSRAVD __m128i _mm_mask_srav_epi32(__m128i s, __mmask8 m, __m128i a, __m128i cnt);VPSRAVD __m128i _mm_maskz_srav_epi32(__mmask8 m, __m128i a, __m128i cnt);VPSRAVQ __m512i _mm512_srav_epi64(__m512i a, __m512i cnt);VPSRAVQ __m512i _mm512_mask_srav_epi64(__m512i s, __mmask8 m, __m512i a, __m512i cnt);VPSRAVQ __m512i _mm512_maskz_srav_epi64( __mmask8 m, __m512i a, __m512i cnt);VPSRAVQ __m256i _mm256_srav_epi64(__m256i a, __m256i cnt);VPSRAVQ __m256i _mm256_mask_srav_epi64(__m256i s, __mmask8 m, __m256i a, __m256i cnt);VPSRAVQ __m256i _mm256_maskz_srav_epi64( __mmask8 m, __m256i a, __m256i cnt);VPSRAVQ __m128i _mm_srav_epi64(__m128i a, __m128i cnt);VPSRAVQ __m128i _mm_mask_srav_epi64(__m128i s, __mmask8 m, __m128i a, __m128i cnt);VPSRAVQ __m128i _mm_maskz_srav_epi64( __mmask8 m, __m128i a, __m128i cnt);VPSRAVW __m512i _mm512_srav_epi16(__m512i a, __m512i cnt);VPSRAVW __m512i _mm512_mask_srav_epi16(__m512i s, __mmask32 m, __m512i a, __m512i cnt);VPSRAVW __m512i _mm512_maskz_srav_epi16(__mmask32 m, __m512i a, __m512i cnt);VPSRAVW __m256i _mm256_srav_epi16(__m256i a, __m256i cnt);VPSRAVW __m256i _mm256_mask_srav_epi16(__m256i s, __mmask16 m, __m256i a, __m256i cnt);VPSRAVW __m256i _mm256_maskz_srav_epi16(__mmask16 m, __m256i a, __m256i cnt);VPSRAVW __m128i _mm_srav_epi16(__m128i a, __m128i cnt);VPSRAVW __m128i _mm_mask_srav_epi16(__m128i s, __mmask8 m, __m128i a, __m128i cnt);VPSRAVW __m128i _mm_maskz_srav_epi32(__mmask8 m, __m128i a, __m128i cnt);VPSRAVD __m256i _mm256_srav_epi32 (__m256i m, __m256i count)SIMD Floating-Point ExceptionsNoneOther ExceptionsNon-EVEX-encoded instruction, see Table2-21, “Type 4 Class Exception Conditions”.EVEX-encoded instruction, see Table2-49, “Type E4 Class Exception Conditions”.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.