VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWordInstruction Operand EncodingDescription VPMOVQW down converts 64-bit integer elements in the source operand (the second operand) into packed double-words using truncation. VPMOVSQW converts signed 64-bit integers into packed signed doublewords using signed saturation. VPMOVUSQW convert unsigned quad-word values into unsigned double-word values using unsigned saturation. The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a 256/128/64-bit memory location.Down-converted doubleword elements are written to the destination operand (the first operand) from the least-significant doubleword. Doubleword elements of the destination operand are updated according to the writemask. Bits (MAXVL-1:256/128/64) of the register destination are zeroed.EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.128.F3.0F38.W0 35 /rVPMOVQD xmm1/m128 {k1}{z}, xmm2AV/VAVX512VLAVX512FConverts 2 packed quad-word integers from xmm2into 2 packed double-word integers in xmm1/m128 with truncation subject to writemask k1.EVEX.128.F3.0F38.W0 25 /rVPMOVSQD xmm1/m64 {k1}{z}, xmm2AV/VAVX512VLAVX512FConverts 2 packed signed quad-word integers from xmm2 into 2 packed signed double-word integers in xmm1/m64 usingsigned saturation subject to writemask k1.EVEX.128.F3.0F38.W0 15 /rVPMOVUSQD xmm1/m64 {k1}{z}, xmm2AV/VAVX512VLAVX512FConverts 2 packed unsigned quad-word integers from xmm2 into 2 packed unsigned double-word integers in xmm1/m64 usingunsigned saturation subject to writemask k1.EVEX.256.F3.0F38.W0 35 /rVPMOVQD xmm1/m128 {k1}{z}, ymm2AV/VAVX512VLAVX512FConverts 4 packed quad-word integers from ymm2into 4 packed double-word integers in xmm1/m128 with truncation subject to writemask k1.EVEX.256.F3.0F38.W0 25 /rVPMOVSQD xmm1/m128 {k1}{z}, ymm2AV/VAVX512VLAVX512FConverts 4 packed signed quad-word integers from ymm2 into 4 packed signed double-word integers in xmm1/m128 usingsigned saturation subject to writemask k1.EVEX.256.F3.0F38.W0 15 /rVPMOVUSQD xmm1/m128 {k1}{z}, ymm2AV/VAVX512VLAVX512FConverts 4 packed unsigned quad-word integers from ymm2 into 4 packed unsigned double-word integers in xmm1/m128 usingunsigned saturation subject to writemask k1.EVEX.512.F3.0F38.W0 35 /rVPMOVQD ymm1/m256 {k1}{z}, zmm2AV/VAVX512FConverts 8 packed quad-word integers from zmm2into 8 packed double-word integers in ymm1/m256 with truncation subject to writemask k1.EVEX.512.F3.0F38.W0 25 /rVPMOVSQD ymm1/m256 {k1}{z}, zmm2AV/VAVX512FConverts 8 packed signed quad-word integers from zmm2 into 8 packed signed double-word integers in ymm1/m256 usingsigned saturation subject to writemask k1.EVEX.512.F3.0F38.W0 15 /rVPMOVUSQD ymm1/m256 {k1}{z}, zmm2AV/VAVX512FConverts 8 packed unsigned quad-word integers from zmm2 into 8 packed unsigned double-word integers in ymm1/m256 usingunsigned saturation subject to writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4AHalf MemModRM:r/m (w)ModRM:reg (r)NANA
This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.