image/svg+xmlVPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert a Mask Register to a Vector RegisterInstruction Operand EncodingDescription Converts a mask register to a vector register. Each element in the destination register is set to all 1’s or all 0’s depending on the value of the corresponding bit in the source mask register.The source operand is a mask register. The destination operand is a ZMM/YMM/XMM register.EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.128.F3.0F38.W0 28 /r VPMOVM2B xmm1, k1RMV/VAVX512VLAVX512BWSets each byte in XMM1 to all 1’s or all 0’s based on the value of the corresponding bit in k1. EVEX.256.F3.0F38.W0 28 /r VPMOVM2B ymm1, k1RMV/VAVX512VLAVX512BWSets each byte in YMM1 to all 1’s or all 0’s based on the value of the corresponding bit in k1. EVEX.512.F3.0F38.W0 28 /r VPMOVM2B zmm1, k1RMV/VAVX512BWSets each byte in ZMM1 to all 1’s or all 0’s based on the value of the corresponding bit in k1. EVEX.128.F3.0F38.W1 28 /r VPMOVM2W xmm1, k1 RMV/VAVX512VLAVX512BWSets each word in XMM1 to all 1’s or all 0’s based on the value of the corresponding bit in k1. EVEX.256.F3.0F38.W1 28 /rVPMOVM2W ymm1, k1 RMV/VAVX512VLAVX512BWSets each word in YMM1 to all 1’s or all 0’s based on the value of the corresponding bit in k1. EVEX.512.F3.0F38.W1 28 /r VPMOVM2W zmm1, k1 RMV/VAVX512BWSets each word in ZMM1 to all 1’s or all 0’s based on the value of the corresponding bit in k1. EVEX.128.F3.0F38.W0 38 /r VPMOVM2D xmm1, k1RMV/VAVX512VLAVX512DQSets each doubleword in XMM1 to all 1’s or all 0’s based on the value of the corresponding bit in k1. EVEX.256.F3.0F38.W0 38 /r VPMOVM2D ymm1, k1RMV/VAVX512VLAVX512DQSets each doubleword in YMM1 to all 1’s or all 0’s based on the value of the corresponding bit in k1. EVEX.512.F3.0F38.W0 38 /r VPMOVM2D zmm1, k1RMV/VAVX512DQSets each doubleword in ZMM1 to all 1’s or all 0’s based on the value of the corresponding bit in k1. EVEX.128.F3.0F38.W1 38 /r VPMOVM2Q xmm1, k1 RMV/VAVX512VLAVX512DQSets each quadword in XMM1 to all 1’s or all 0’s based on the value of the corresponding bit in k1. EVEX.256.F3.0F38.W1 38 /r VPMOVM2Q ymm1, k1 RMV/VAVX512VLAVX512DQSets each quadword in YMM1 to all 1’s or all 0’s based on the value of the corresponding bit in k1. EVEX.512.F3.0F38.W1 38 /r VPMOVM2Q zmm1, k1 RMV/VAVX512DQSets each quadword in ZMM1 to all 1’s or all 0’s based on the value of the corresponding bit in k1. Op/EnOperand 1Operand 2Operand 3Operand 4RMModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlOperationVPMOVM2B (EVEX encoded versions) (KL, VL) = (16, 128), (32, 256), (64, 512)FOR j := 0 TO KL-1i := j * 8IF SRC[j]THEN DEST[i+7:i] := -1 ELSE DEST[i+7:i] := 0FI;ENDFORDEST[MAXVL-1:VL] := 0VPMOVM2W (EVEX encoded versions) (KL, VL) = (8, 128), (16, 256), (32, 512)FOR j := 0 TO KL-1i := j * 16IF SRC[j]THEN DEST[i+15:i] := -1 ELSE DEST[i+15:i] := 0FI;ENDFORDEST[MAXVL-1:VL] := 0VPMOVM2D (EVEX encoded versions) (KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF SRC[j]THEN DEST[i+31:i] := -1 ELSE DEST[i+31:i] := 0FI;ENDFORDEST[MAXVL-1:VL] := 0VPMOVM2Q (EVEX encoded versions) (KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64IF SRC[j]THEN DEST[i+63:i] := -1 ELSE DEST[i+63:i] := 0FI;ENDFORDEST[MAXVL-1:VL] := 0

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentsVPMOVM2B __m512i _mm512_movm_epi8(__mmask64 );VPMOVM2D __m512i _mm512_movm_epi32(__mmask8 );VPMOVM2Q __m512i _mm512_movm_epi64(__mmask16 );VPMOVM2W __m512i _mm512_movm_epi16(__mmask32 );VPMOVM2B __m256i _mm256_movm_epi8(__mmask32 );VPMOVM2D __m256i _mm256_movm_epi32(__mmask8 );VPMOVM2Q __m256i _mm256_movm_epi64(__mmask8 );VPMOVM2W __m256i _mm256_movm_epi16(__mmask16 );VPMOVM2B __m128i _mm_movm_epi8(__mmask16 );VPMOVM2D __m128i _mm_movm_epi32(__mmask8 );VPMOVM2Q __m128i _mm_movm_epi64(__mmask8 );VPMOVM2W __m128i _mm_movm_epi16(__mmask8 );SIMD Floating-Point ExceptionsNoneOther ExceptionsEVEX-encoded instruction, see Table2-55, “Type E7NM Class Exception Conditions”; additionally:#UD If EVEX.vvvv != 1111B.

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