image/svg+xmlVPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to ByteInstruction Operand EncodingDescription VPMOVDB down converts 32-bit integer elements in the source operand (the second operand) into packed bytes using truncation. VPMOVSDB converts signed 32-bit integers into packed signed bytes using signed saturation. VPMOVUSDB convert unsigned double-word values into unsigned byte values using unsigned saturation. The source operand is a ZMM/YMM/XMM register. The destination operand is a XMM register or a 128/64/32-bit memory location.Down-converted byte elements are written to the destination operand (the first operand) from the least-significant byte. Byte elements of the destination operand are updated according to the writemask. Bits (MAXVL-1:128/64/32) of the register destination are zeroed.EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.128.F3.0F38.W0 31 /rVPMOVDB xmm1/m32 {k1}{z}, xmm2AV/VAVX512VLAVX512FConverts 4 packed double-word integers from xmm2 into 4 packed byte integers in xmm1/m32 with truncation under writemask k1.EVEX.128.F3.0F38.W0 21 /rVPMOVSDB xmm1/m32 {k1}{z}, xmm2AV/VAVX512VLAVX512FConverts 4 packed signed double-word integers from xmm2 into 4 packed signed byte integers in xmm1/m32 using signed saturation under writemask k1.EVEX.128.F3.0F38.W0 11 /rVPMOVUSDB xmm1/m32 {k1}{z}, xmm2AV/VAVX512VLAVX512FConverts 4 packed unsigned double-word integers from xmm2 into 4 packed unsigned byte integers in xmm1/m32 using unsigned saturation under writemask k1.EVEX.256.F3.0F38.W0 31 /rVPMOVDB xmm1/m64 {k1}{z}, ymm2AV/VAVX512VLAVX512FConverts 8 packed double-word integers from ymm2 into 8 packed byte integers in xmm1/m64 with truncation under writemask k1.EVEX.256.F3.0F38.W0 21 /rVPMOVSDB xmm1/m64 {k1}{z}, ymm2AV/VAVX512VLAVX512FConverts 8 packed signed double-word integers from ymm2 into 8 packed signed byte integers in xmm1/m64 using signed saturation under writemask k1.EVEX.256.F3.0F38.W0 11 /rVPMOVUSDB xmm1/m64 {k1}{z}, ymm2AV/VAVX512VLAVX512FConverts 8 packed unsigned double-word integers from ymm2 into 8 packed unsigned byte integers in xmm1/m64 using unsigned saturation under writemask k1.EVEX.512.F3.0F38.W0 31 /rVPMOVDB xmm1/m128 {k1}{z}, zmm2AV/VAVX512FConverts 16 packed double-word integers from zmm2 into 16 packed byte integers in xmm1/m128 with truncation under writemask k1.EVEX.512.F3.0F38.W0 21 /rVPMOVSDB xmm1/m128 {k1}{z}, zmm2AV/VAVX512FConverts 16 packed signed double-word integers from zmm2 into 16 packed signed byte integers in xmm1/m128 using signed saturation under writemask k1.EVEX.512.F3.0F38.W0 11 /rVPMOVUSDB xmm1/m128 {k1}{z}, zmm2AV/VAVX512FConverts 16 packed unsigned double-word integers from zmm2 into 16 packed unsigned byte integers in xmm1/m128 using unsigned saturation under writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4AQuarter MemModRM:r/m (w)ModRM:reg (r)NANA

image/svg+xmlOperationVPMOVDB instruction (EVEX encoded versions) when dest is a register(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 8m := j * 32IF k1[j] OR *no writemask*THEN DEST[i+7:i] := TruncateDoubleWordToByte (SRC[m+31:m])ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+7:i] remains unchanged*ELSE *zeroing-masking*; zeroing-maskingDEST[i+7:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL/4] := 0;VPMOVDB instruction (EVEX encoded versions) when dest is memory(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 8m := j * 32IF k1[j] OR *no writemask*THEN DEST[i+7:i] := TruncateDoubleWordToByte (SRC[m+31:m])ELSE *DEST[i+7:i] remains unchanged*; merging-maskingFI;ENDFORVPMOVSDB instruction (EVEX encoded versions) when dest is a register(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 8m := j * 32IF k1[j] OR *no writemask*THEN DEST[i+7:i] := SaturateSignedDoubleWordToByte (SRC[m+31:m])ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+7:i] remains unchanged*ELSE *zeroing-masking*; zeroing-maskingDEST[i+7:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL/4] := 0;

image/svg+xmlVPMOVSDB instruction (EVEX encoded versions) when dest is memory(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 8m := j * 32IF k1[j] OR *no writemask*THEN DEST[i+7:i] := SaturateSignedDoubleWordToByte (SRC[m+31:m])ELSE *DEST[i+7:i] remains unchanged*; merging-maskingFI;ENDFORVPMOVUSDB instruction (EVEX encoded versions) when dest is a register(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 8m := j * 32IF k1[j] OR *no writemask*THEN DEST[i+7:i] := SaturateUnsignedDoubleWordToByte (SRC[m+31:m])ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+7:i] remains unchanged*ELSE *zeroing-masking*; zeroing-maskingDEST[i+7:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL/4] := 0;VPMOVUSDB instruction (EVEX encoded versions) when dest is memory(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 8m := j * 32IF k1[j] OR *no writemask*THEN DEST[i+7:i] := SaturateUnsignedDoubleWordToByte (SRC[m+31:m])ELSE *DEST[i+7:i] remains unchanged*; merging-maskingFI;ENDFOR

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentsVPMOVDB __m128i _mm512_cvtepi32_epi8( __m512i a);VPMOVDB __m128i _mm512_mask_cvtepi32_epi8(__m128i s, __mmask16 k, __m512i a);VPMOVDB __m128i _mm512_maskz_cvtepi32_epi8( __mmask16 k, __m512i a);VPMOVDB void _mm512_mask_cvtepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);VPMOVSDB __m128i _mm512_cvtsepi32_epi8( __m512i a);VPMOVSDB __m128i _mm512_mask_cvtsepi32_epi8(__m128i s, __mmask16 k, __m512i a);VPMOVSDB __m128i _mm512_maskz_cvtsepi32_epi8( __mmask16 k, __m512i a);VPMOVSDB void _mm512_mask_cvtsepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);VPMOVUSDB __m128i _mm512_cvtusepi32_epi8( __m512i a);VPMOVUSDB __m128i _mm512_mask_cvtusepi32_epi8(__m128i s, __mmask16 k, __m512i a);VPMOVUSDB __m128i _mm512_maskz_cvtusepi32_epi8( __mmask16 k, __m512i a);VPMOVUSDB void _mm512_mask_cvtusepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);VPMOVUSDB __m128i _mm256_cvtusepi32_epi8(__m256i a);VPMOVUSDB __m128i _mm256_mask_cvtusepi32_epi8(__m128i a, __mmask8 k, __m256i b);VPMOVUSDB __m128i _mm256_maskz_cvtusepi32_epi8( __mmask8 k, __m256i b);VPMOVUSDB void _mm256_mask_cvtusepi32_storeu_epi8(void * , __mmask8 k, __m256i b);VPMOVUSDB __m128i _mm_cvtusepi32_epi8(__m128i a);VPMOVUSDB __m128i _mm_mask_cvtusepi32_epi8(__m128i a, __mmask8 k, __m128i b);VPMOVUSDB __m128i _mm_maskz_cvtusepi32_epi8( __mmask8 k, __m128i b);VPMOVUSDB void _mm_mask_cvtusepi32_storeu_epi8(void * , __mmask8 k, __m128i b);VPMOVSDB __m128i _mm256_cvtsepi32_epi8(__m256i a);VPMOVSDB __m128i _mm256_mask_cvtsepi32_epi8(__m128i a, __mmask8 k, __m256i b);VPMOVSDB __m128i _mm256_maskz_cvtsepi32_epi8( __mmask8 k, __m256i b);VPMOVSDB void _mm256_mask_cvtsepi32_storeu_epi8(void * , __mmask8 k, __m256i b);VPMOVSDB __m128i _mm_cvtsepi32_epi8(__m128i a);VPMOVSDB __m128i _mm_mask_cvtsepi32_epi8(__m128i a, __mmask8 k, __m128i b);VPMOVSDB __m128i _mm_maskz_cvtsepi32_epi8( __mmask8 k, __m128i b);VPMOVSDB void _mm_mask_cvtsepi32_storeu_epi8(void * , __mmask8 k, __m128i b);VPMOVDB __m128i _mm256_cvtepi32_epi8(__m256i a);VPMOVDB __m128i _mm256_mask_cvtepi32_epi8(__m128i a, __mmask8 k, __m256i b);VPMOVDB __m128i _mm256_maskz_cvtepi32_epi8( __mmask8 k, __m256i b);VPMOVDB void _mm256_mask_cvtepi32_storeu_epi8(void * , __mmask8 k, __m256i b);VPMOVDB __m128i _mm_cvtepi32_epi8(__m128i a);VPMOVDB __m128i _mm_mask_cvtepi32_epi8(__m128i a, __mmask8 k, __m128i b);VPMOVDB __m128i _mm_maskz_cvtepi32_epi8( __mmask8 k, __m128i b);VPMOVDB void _mm_mask_cvtepi32_storeu_epi8(void * , __mmask8 k, __m128i b);SIMD Floating-Point ExceptionsNoneOther ExceptionsEVEX-encoded instruction, see Table2-53, “Type E6 Class Exception Conditions”; additionally:#UD If EVEX.vvvv != 1111B.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.