image/svg+xmlVPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a Mask Instruction Operand EncodingDescription Converts a vector register to a mask register. Each element in the destination register is set to 1 or 0 depending on the value of most significant bit of the corresponding element in the source register.The source operand is a ZMM/YMM/XMM register. The destination operand is a mask register.EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.128.F3.0F38.W0 29 /r VPMOVB2M k1, xmm1RMV/VAVX512VLAVX512BWSets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding byte in XMM1. EVEX.256.F3.0F38.W0 29 /r VPMOVB2M k1, ymm1RMV/VAVX512VLAVX512BWSets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding byte in YMM1. EVEX.512.F3.0F38.W0 29 /r VPMOVB2M k1, zmm1 RMV/VAVX512BWSets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding byte in ZMM1. EVEX.128.F3.0F38.W1 29 /r VPMOVW2M k1, xmm1 RMV/VAVX512VLAVX512BWSets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding word in XMM1. EVEX.256.F3.0F38.W1 29 /r VPMOVW2M k1, ymm1RMV/VAVX512VLAVX512BWSets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding word in YMM1. EVEX.512.F3.0F38.W1 29 /r VPMOVW2M k1, zmm1RMV/VAVX512BWSets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding word in ZMM1. EVEX.128.F3.0F38.W0 39 /r VPMOVD2M k1, xmm1 RMV/VAVX512VLAVX512DQSets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding doubleword in XMM1. EVEX.256.F3.0F38.W0 39 /r VPMOVD2M k1, ymm1 RMV/VAVX512VLAVX512DQSets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding doubleword in YMM1. EVEX.512.F3.0F38.W0 39 /r VPMOVD2M k1, zmm1RMV/VAVX512DQSets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding doubleword in ZMM1. EVEX.128.F3.0F38.W1 39 /r VPMOVQ2M k1, xmm1 RMV/VAVX512VLAVX512DQSets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding quadword in XMM1. EVEX.256.F3.0F38.W1 39 /r VPMOVQ2M k1, ymm1 RMV/VAVX512VLAVX512DQSets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding quadword in YMM1. EVEX.512.F3.0F38.W1 39 /r VPMOVQ2M k1, zmm1 RMV/VAVX512DQSets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding quadword in ZMM1. Op/EnOperand 1Operand 2Operand 3Operand 4RMModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlOperationVPMOVB2M (EVEX encoded versions) (KL, VL) = (16, 128), (32, 256), (64, 512)FOR j := 0 TO KL-1i := j * 8IF SRC[i+7]THEN DEST[j] := 1 ELSE DEST[j] := 0FI;ENDFORDEST[MAX_KL-1:KL] := 0VPMOVW2M (EVEX encoded versions) (KL, VL) = (8, 128), (16, 256), (32, 512)FOR j := 0 TO KL-1i := j * 16IF SRC[i+15]THEN DEST[j] := 1 ELSE DEST[j] := 0FI;ENDFORDEST[MAX_KL-1:KL] := 0VPMOVD2M (EVEX encoded versions) (KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF SRC[i+31]THEN DEST[j] := 1 ELSE DEST[j] := 0FI;ENDFORDEST[MAX_KL-1:KL] := 0VPMOVQ2M (EVEX encoded versions) (KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64IF SRC[i+63]THEN DEST[j] := 1 ELSE DEST[j] := 0FI;ENDFORDEST[MAX_KL-1:KL] := 0

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentsVPMPOVB2M __mmask64 _mm512_movepi8_mask( __m512i );VPMPOVD2M __mmask16 _mm512_movepi32_mask( __m512i );VPMPOVQ2M __mmask8 _mm512_movepi64_mask( __m512i );VPMPOVW2M __mmask32 _mm512_movepi16_mask( __m512i );VPMPOVB2M __mmask32 _mm256_movepi8_mask( __m256i );VPMPOVD2M __mmask8 _mm256_movepi32_mask( __m256i );VPMPOVQ2M __mmask8 _mm256_movepi64_mask( __m256i );VPMPOVW2M __mmask16 _mm256_movepi16_mask( __m256i );VPMPOVB2M __mmask16 _mm_movepi8_mask( __m128i );VPMPOVD2M __mmask8 _mm_movepi32_mask( __m128i );VPMPOVQ2M __mmask8 _mm_movepi64_mask( __m128i );VPMPOVW2M __mmask8 _mm_movepi16_mask( __m128i );SIMD Floating-Point ExceptionsNoneOther ExceptionsEVEX-encoded instruction, see Table2-55, “Type E7NM Class Exception Conditions”; additionally:#UD If EVEX.vvvv != 1111B.

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