VPMADD52LUQ—Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Qword AccumulatorsInstruction Operand EncodingDescriptionMultiplies packed unsigned 52-bit integers in each qword element of the first source operand (the second oper-and) with the packed unsigned 52-bit integers in the corresponding elements of the second source operand (the third operand) to form packed 104-bit intermediate results. The low 52-bit, unsigned integer of each 104-bit product is added to the corresponding qword unsigned integer of the destination operand (the first operand) under the writemask k1.The first source operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM reg-ister, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory loca-tion. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1 at 64-bit granularity.Opcode/InstructionOp/En32/64 bit Mode SupportCPUIDDescriptionEVEX.128.66.0F38.W1 B4 /rVPMADD52LUQ xmm1 {k1}{z}, xmm2,xmm3/m128/m64bcstAV/V AVX512_IFMAAVX512VLMultiply unsigned 52-bit integers in xmm2 and xmm3/m128 and add the low 52 bits of the 104-bit product to the qword unsigned integers in xmm1 using writemask k1.EVEX.256.66.0F38.W1 B4 /rVPMADD52LUQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstAV/V AVX512_IFMAAVX512VLMultiply unsigned 52-bit integers in ymm2 and ymm3/m256 and add the low 52 bits of the 104-bit product to the qword unsigned integers in ymm1 using writemask k1.EVEX.512.66.0F38.W1 B4 /rVPMADD52LUQ zmm1 {k1}{z}, zmm2,zmm3/m512/m64bcstAV/V AVX512_IFMAMultiply unsigned 52-bit integers in zmm2 and zmm3/m512 and add the low 52 bits of the 104-bit product to the qword unsigned integers in zmm1 using writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4AFullModRM:reg (r, w)EVEX.vvvv (r)ModRM:r/m(r)NA
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