image/svg+xml VPEXPANDD—Load Sparse Packed Doubleword Integer Values from Dense Memory / Register Instruction Operand Encoding Description Expand (load) up to 16 contiguous doubleword integer values of the input vector in the source operand (the second operand) to sparse elements in the destination operand (the first operand), selected by the writemask k1. The destination operand is a ZMM register, the source operand can be a ZMM register or memory location. The input vector starts from the lowest element in the source operand. The opmask register k1 selects the destina- tion elements (a partial vector or sparse elements if less than 8 elements) to be replaced by the ascending elements in the input vector. Destination elements not selected by the writemask k1 are either unmodified or zeroed, depending on EVEX.z. Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element instead of the size of the full vector. Operation VPEXPANDD (EVEX encoded versions) (KL, VL) = (4, 128), (8, 256), (16, 512) k := 0 FOR j := 0 TO KL-1 i := j * 32 IF k1[j] OR *no writemask* THEN DEST[i+31:i] := SRC[k+31:k]; k := k + 32 ELSE IF *merging-masking*; merging-masking THEN *DEST[i+31:i] remains unchanged* ELSE ; zeroing-masking DEST[i+31:i] := 0 FI FI; ENDFOR DEST[MAXVL-1:VL] := 0 Opcode/ Instruction Op/ En 64/32 bit Mode Support CPUID Feature Flag Description EVEX.128.66.0F38.W0 89 /r VPEXPANDD xmm1 {k1}{z}, xmm2/m128 AV/VAVX512VL AVX512F Expand packed double-word integer values from xmm2/m128 to xmm1 using writemask k1. EVEX.256.66.0F38.W0 89 /r VPEXPANDD ymm1 {k1}{z}, ymm2/m256 AV/VAVX512VL AVX512F Expand packed double-word integer values from ymm2/m256 to ymm1 using writemask k1. EVEX.512.66.0F38.W0 89 /r VPEXPANDD zmm1 {k1}{z}, zmm2/m512 AV/VAVX512FExpand packed double-word integer values from zmm2/m512 to zmm1 using writemask k1. Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4 ATuple1 ScalarModRM:reg (w)ModRM:r/m (r)NANA image/svg+xml Intel C/C++ Compiler Intrinsic Equivalent VPEXPANDD __m512i _mm512_mask_expandloadu_epi32(__m512i s, __mmask16 k, void * a); VPEXPANDD __m512i _mm512_maskz_expandloadu_epi32( __mmask16 k, void * a); VPEXPANDD __m512i _mm512_mask_expand_epi32(__m512i s, __mmask16 k, __m512i a); VPEXPANDD __m512i _mm512_maskz_expand_epi32( __mmask16 k, __m512i a); VPEXPANDD __m256i _mm256_mask_expandloadu_epi32(__m256i s, __mmask8 k, void * a); VPEXPANDD __m256i _mm256_maskz_expandloadu_epi32( __mmask8 k, void * a); VPEXPANDD __m256i _mm256_mask_expand_epi32(__m256i s, __mmask8 k, __m256i a); VPEXPANDD __m256i _mm256_maskz_expand_epi32( __mmask8 k, __m256i a); VPEXPANDD __m128i _mm_mask_expandloadu_epi32(__m128i s, __mmask8 k, void * a); VPEXPANDD __m128i _mm_maskz_expandloadu_epi32( __mmask8 k, void * a); VPEXPANDD __m128i _mm_mask_expand_epi32(__m128i s, __mmask8 k, __m128i a); VPEXPANDD __m128i _mm_maskz_expand_epi32( __mmask8 k, __m128i a); SIMD Floating-Point Exceptions None Other Exceptions EVEX-encoded instruction, see Exceptions Type E4.nb in Table2-49, “Type E4 Class Exception Conditions”; additionally: #UDIf EVEX.vvvv != 1111B. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .