VPERMPD—Permute Double-Precision Floating-Point ElementsInstruction Operand EncodingDescriptionThe imm8 version: Copies quadword elements of double-precision floating-point values from the source operand (the second operand) to the destination operand (the first operand) according to the indices specified by the imme-diate operand (the third operand). Each two-bit value in the immediate byte selects a qword element in the source operand. VEX version: The source operand can be a YMM register or a memory location. Bits (MAXVL-1:256) of the corre-sponding destination register are zeroed.In EVEX.512 encoded version, The elements in the destination are updated using the writemask k1 and the imm8 bits are reused as control bits for the upper 256-bit half when the control bits are coming from immediate. The source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit memory location.The imm8 versions: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.The vector control version: Copies quadword elements of double-precision floating-point values from the second source operand (the third operand) to the destination operand (the first operand) according to the indices in the first source operand (the second operand). The first 3 bits of each 64 bit element in the index operand selects which quadword in the second source operand to copy. The first and second operands are ZMM registers, the third operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit memory location. The elements in the destination are updated using the writemask k1.Note that this instruction permits a qword in the source operand to be copied to multiple locations in the destination operand. If VPERMPD is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will cause an #UD exception.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionVEX.256.66.0F3A.W1 01 /r ibVPERMPD ymm1, ymm2/m256, imm8AV/VAVX2Permute double-precision floating-point elements in ymm2/m256 using indices in imm8 and store the result in ymm1.EVEX.256.66.0F3A.W1 01 /r ibVPERMPD ymm1 {k1}{z}, ymm2/m256/m64bcst, imm8BV/VAVX512VLAVX512FPermute double-precision floating-point elements in ymm2/m256/m64bcst using indexes in imm8 and store the result in ymm1 subject to writemask k1.EVEX.512.66.0F3A.W1 01 /r ibVPERMPD zmm1 {k1}{z}, zmm2/m512/m64bcst, imm8BV/VAVX512FPermute double-precision floating-point elements in zmm2/m512/m64bcst using indices in imm8 and store the result in zmm1 subject to writemask k1.EVEX.256.66.0F38.W1 16 /rVPERMPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstCV/VAVX512VLAVX512FPermute double-precision floating-point elements in ymm3/m256/m64bcst using indexes in ymm2 and store the result in ymm1 subject to writemask k1.EVEX.512.66.0F38.W1 16 /r VPERMPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstCV/VAVX512FPermute double-precision floating-point elements in zmm3/m512/m64bcst using indices in zmm2 and store the result in zmm1 subject to writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)Imm8NABFullModRM:reg (w)ModRM:r/m (r)Imm8NACFullModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA
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