image/svg+xmlVPDPWSSD — Multiply and Add Signed Word IntegersInstruction Operand EncodingDescriptionMultiplies the individual signed words of the first source operand by the corresponding signed words of the second source operand, producing intermediate signed, doubleword results. The adjacent doubleword results are then summed and accumulated in the destination operand.This instruction supports memory fault suppression.OperationVPDPWSSD dest, src1, src2 (VEX encoded versions)VL=(128, 256)KL=VL/32ORIGDEST := DESTFOR i := 0 TO KL-1:p1dword := SIGN_EXTEND(SRC1.word[2*i+0]) * SIGN_EXTEND(SRC2.word[2*i+0] )p2dword := SIGN_EXTEND(SRC1.word[2*i+1]) * SIGN_EXTEND(SRC2.word[2*i+1] )DEST.dword[i] := ORIGDEST.dword[i] + p1dword + p2dwordDEST[MAX_VL-1:VL] := 0Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionVEX.128.66.0F38.W0 52 /r VPDPWSSD xmm1, xmm2, xmm3/m128AV/VAVX-VNNIMultiply groups of 2 pairs signed words in xmm3/m128 with corresponding signed words of xmm2, summing those products and adding them to doubleword result in xmm1.VEX.256.66.0F38.W0 52 /rVPDPWSSD ymm1, ymm2, ymm3/m256AV/VAVX-VNNIMultiply groups of 2 pairs signed words in ymm3/m256 with corresponding signed words of ymm2, summing those products and adding them to doubleword result in ymm1.EVEX.128.66.0F38.W0 52 /rVPDPWSSD xmm1{k1}{z}, xmm2, xmm3/m128/m32bcstBV/VAVX512_VNNIAVX512VLMultiply groups of 2 pairs signed words in xmm3/m128/m32bcst with corresponding signed words of xmm2, summing those products and adding them to doubleword result in xmm1, under writemask k1.EVEX.256.66.0F38.W0 52 /rVPDPWSSD ymm1{k1}{z}, ymm2, ymm3/m256/m32bcstBV/VAVX512_VNNIAVX512VLMultiply groups of 2 pairs signed words in ymm3/m256/m32bcst with corresponding signed words of ymm2, summing those products and adding them to doubleword result in ymm1, under writemask k1.EVEX.512.66.0F38.W0 52 /rVPDPWSSD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcstBV/VAVX512_VNNIMultiply groups of 2 pairs signed words in zmm3/m512/m32bcst with corresponding signed words of zmm2, summing those products and adding them to doubleword result in zmm1, under writemask k1.Op/EnTupleOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)VEX.vvvv (r)ModRM:r/m (r)NABFullModRM:reg (r, w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlVPDPWSSD dest, src1, src2 (EVEX encoded versions)(KL,VL)=(4,128), (8,256), (16,512)ORIGDEST := DESTFOR i := 0 TO KL-1:IF k1[i] or *no writemask*:IF SRC2 is memory and EVEX.b == 1:t := SRC2.dword[0]ELSE:t := SRC2.dword[i]p1dword := SIGN_EXTEND(SRC1.word[2*i]) * SIGN_EXTEND(t.word[0])p2dword := SIGN_EXTEND(SRC1.word[2*i+1]) * SIGN_EXTEND(t.word[1])DEST.dword[i] := ORIGDEST.dword[i] + p1dword + p2dwordELSE IF *zeroing*:DEST.dword[i] := 0ELSE: // Merge masking, dest element unchangedDEST.dword[i] := ORIGDEST.dword[i]DEST[MAX_VL-1:VL] := 0Intel C/C++ Compiler Intrinsic EquivalentVPDPWSSD __m128i _mm_dpwssd_avx_epi32(__m128i, __m128i, __m128i);VPDPWSSD __m128i _mm_dpwssd_epi32(__m128i, __m128i, __m128i);VPDPWSSD __m128i _mm_mask_dpwssd_epi32(__m128i, __mmask8, __m128i, __m128i);VPDPWSSD __m128i _mm_maskz_dpwssd_epi32(__mmask8, __m128i, __m128i, __m128i);VPDPWSSD __m256i _mm256_dpwssd_avx_epi32(__m256i, __m256i, __m256i);VPDPWSSD __m256i _mm256_dpwssd_epi32(__m256i, __m256i, __m256i);VPDPWSSD __m256i _mm256_mask_dpwssd_epi32(__m256i, __mmask8, __m256i, __m256i);VPDPWSSD __m256i _mm256_maskz_dpwssd_epi32(__mmask8, __m256i, __m256i, __m256i);VPDPWSSD __m512i _mm512_dpwssd_epi32(__m512i, __m512i, __m512i);VPDPWSSD __m512i _mm512_mask_dpwssd_epi32(__m512i, __mmask16, __m512i, __m512i);VPDPWSSD __m512i _mm512_maskz_dpwssd_epi32(__mmask16, __m512i, __m512i, __m512i);SIMD Floating-Point ExceptionsNone.Other ExceptionsNon-EVEX-encoded instruction, see Table2-21, “Type 4 Class Exception Conditions”.EVEX-encoded instruction, see Table2-49, “Type E4 Class Exception Conditions”.

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