image/svg+xmlVPCONFLICTD/Q—Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense Memory/ RegisterInstruction Operand EncodingDescriptionTest each dword/qword element of the source operand (the second operand) for equality with all other elements in the source operand closer to the least significant element. Each element’s comparison results form a bit vector, which is then zero extended and written to the destination according to the writemask.EVEX.512 encoded version: The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1. EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a YMM register, conditionally updated using writemask k1. EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a XMM register, conditionally updated using writemask k1. EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.128.66.0F38.W0 C4 /rVPCONFLICTD xmm1 {k1}{z}, xmm2/m128/m32bcstAV/V AVX512VLAVX512CDDetect duplicate double-word values in xmm2/m128/m32bcst using writemask k1.EVEX.256.66.0F38.W0 C4 /rVPCONFLICTD ymm1 {k1}{z}, ymm2/m256/m32bcstAV/V AVX512VLAVX512CDDetect duplicate double-word values in ymm2/m256/m32bcst using writemask k1.EVEX.512.66.0F38.W0 C4 /rVPCONFLICTD zmm1 {k1}{z}, zmm2/m512/m32bcstAV/V AVX512CDDetect duplicate double-word values in zmm2/m512/m32bcst using writemask k1.EVEX.128.66.0F38.W1 C4 /rVPCONFLICTQ xmm1 {k1}{z}, xmm2/m128/m64bcstAV/V AVX512VLAVX512CDDetect duplicate quad-word values in xmm2/m128/m64bcst using writemask k1.EVEX.256.66.0F38.W1 C4 /rVPCONFLICTQ ymm1 {k1}{z}, ymm2/m256/m64bcstAV/V AVX512VLAVX512CDDetect duplicate quad-word values in ymm2/m256/m64bcst using writemask k1.EVEX.512.66.0F38.W1 C4 /rVPCONFLICTQ zmm1 {k1}{z}, zmm2/m512/m64bcstAV/V AVX512CDDetect duplicate quad-word values in zmm2/m512/m64bcst using writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4AFullModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlOperationVPCONFLICTD(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j*32IF MaskBit(j) OR *no writemask*THEN FOR k := 0 TO j-1m := k*32IF ((SRC[i+31:i] = SRC[m+31:m])) THEN DEST[i+k] := 1ELSE DEST[i+k] := 0FIENDFORDEST[i+31:i+j] := 0ELSEIF *merging-masking* THEN *DEST[i+31:i] remains unchanged*ELSE DEST[i+31:i] := 0FIFIENDFORDEST[MAXVL-1:VL] := 0VPCONFLICTQ(KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j*64IF MaskBit(j) OR *no writemask*THEN FOR k := 0 TO j-1m := k*64IF ((SRC[i+63:i] = SRC[m+63:m])) THEN DEST[i+k] := 1ELSE DEST[i+k] := 0FIENDFORDEST[i+63:i+j] := 0ELSEIF *merging-masking* THEN *DEST[i+63:i] remains unchanged*ELSEDEST[i+63:i] := 0 FIFIENDFORDEST[MAXVL-1:VL] := 0

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentVPCONFLICTD __m512i _mm512_conflict_epi32( __m512i a);VPCONFLICTD __m512i _mm512_mask_conflict_epi32(__m512i s, __mmask16 m, __m512i a);VPCONFLICTD __m512i _mm512_maskz_conflict_epi32(__mmask16 m, __m512i a);VPCONFLICTQ __m512i _mm512_conflict_epi64( __m512i a);VPCONFLICTQ __m512i _mm512_mask_conflict_epi64(__m512i s, __mmask8 m, __m512i a);VPCONFLICTQ __m512i _mm512_maskz_conflict_epi64(__mmask8 m, __m512i a);VPCONFLICTD __m256i _mm256_conflict_epi32( __m256i a);VPCONFLICTD __m256i _mm256_mask_conflict_epi32(__m256i s, __mmask8 m, __m256i a);VPCONFLICTD __m256i _mm256_maskz_conflict_epi32(__mmask8 m, __m256i a);VPCONFLICTQ __m256i _mm256_conflict_epi64( __m256i a);VPCONFLICTQ __m256i _mm256_mask_conflict_epi64(__m256i s, __mmask8 m, __m256i a);VPCONFLICTQ __m256i _mm256_maskz_conflict_epi64(__mmask8 m, __m256i a);VPCONFLICTD __m128i _mm_conflict_epi32( __m128i a);VPCONFLICTD __m128i _mm_mask_conflict_epi32(__m128i s, __mmask8 m, __m128i a);VPCONFLICTD __m128i _mm_maskz_conflict_epi32(__mmask8 m, __m128i a);VPCONFLICTQ __m128i _mm_conflict_epi64( __m128i a);VPCONFLICTQ __m128i _mm_mask_conflict_epi64(__m128i s, __mmask8 m, __m128i a);VPCONFLICTQ __m128i _mm_maskz_conflict_epi64(__mmask8 m, __m128i a);SIMD Floating-Point ExceptionsNoneOther ExceptionsEVEX-encoded instruction, see Table2-50, “Type E4NF Class Exception Conditions”.

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