image/svg+xmlVPBROADCAST—Load Integer and BroadcastOpcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionVEX.128.66.0F38.W0 78 /rVPBROADCASTB xmm1, xmm2/m8AV/VAVX2Broadcast a byte integer in the source operand to sixteen locations in xmm1.VEX.256.66.0F38.W0 78 /rVPBROADCASTB ymm1, xmm2/m8AV/VAVX2Broadcast a byte integer in the source operand to thirty-two locations in ymm1.EVEX.128.66.0F38.W0 78 /rVPBROADCASTB xmm1{k1}{z}, xmm2/m8BV/VAVX512VLAVX512BWBroadcast a byte integer in the source operand to locations in xmm1 subject to writemask k1.EVEX.256.66.0F38.W0 78 /rVPBROADCASTB ymm1{k1}{z}, xmm2/m8BV/VAVX512VLAVX512BWBroadcast a byte integer in the source operand to locations in ymm1 subject to writemask k1.EVEX.512.66.0F38.W0 78 /rVPBROADCASTB zmm1{k1}{z}, xmm2/m8BV/VAVX512BWBroadcast a byte integer in the source operand to 64 locations in zmm1 subject to writemask k1.VEX.128.66.0F38.W0 79 /rVPBROADCASTW xmm1, xmm2/m16AV/VAVX2Broadcast a word integer in the source operand to eight locations in xmm1.VEX.256.66.0F38.W0 79 /rVPBROADCASTW ymm1, xmm2/m16AV/VAVX2Broadcast a word integer in the source operand to sixteen locations in ymm1.EVEX.128.66.0F38.W0 79 /rVPBROADCASTW xmm1{k1}{z}, xmm2/m16BV/VAVX512VLAVX512BWBroadcast a word integer in the source operand to locations in xmm1 subject to writemask k1.EVEX.256.66.0F38.W0 79 /rVPBROADCASTW ymm1{k1}{z}, xmm2/m16BV/VAVX512VLAVX512BWBroadcast a word integer in the source operand to locations in ymm1 subject to writemask k1.EVEX.512.66.0F38.W0 79 /rVPBROADCASTW zmm1{k1}{z}, xmm2/m16BV/VAVX512BWBroadcast a word integer in the source operand to 32 locations in zmm1 subject to writemask k1.VEX.128.66.0F38.W0 58 /rVPBROADCASTD xmm1, xmm2/m32AV/VAVX2Broadcast a dword integer in the source operand to four locations in xmm1.VEX.256.66.0F38.W0 58 /rVPBROADCASTD ymm1, xmm2/m32AV/VAVX2Broadcast a dword integer in the source operand to eight locations in ymm1.EVEX.128.66.0F38.W0 58 /rVPBROADCASTD xmm1 {k1}{z}, xmm2/m32BV/VAVX512VLAVX512FBroadcast a dword integer in the source operand to locations in xmm1 subject to writemask k1.EVEX.256.66.0F38.W0 58 /rVPBROADCASTD ymm1 {k1}{z}, xmm2/m32BV/VAVX512VLAVX512FBroadcast a dword integer in the source operand to locations in ymm1 subject to writemask k1.EVEX.512.66.0F38.W0 58 /rVPBROADCASTD zmm1 {k1}{z}, xmm2/m32BV/VAVX512FBroadcast a dword integer in the source operand to locations in zmm1 subject to writemask k1.VEX.128.66.0F38.W0 59 /rVPBROADCASTQ xmm1, xmm2/m64AV/VAVX2Broadcast a qword element in source operand to two locations in xmm1.VEX.256.66.0F38.W0 59 /rVPBROADCASTQ ymm1, xmm2/m64AV/VAVX2Broadcast a qword element in source operand to four locations in ymm1.EVEX.128.66.0F38.W1 59 /rVPBROADCASTQ xmm1 {k1}{z}, xmm2/m64BV/VAVX512VLAVX512FBroadcast a qword element in source operand to locations in xmm1 subject to writemask k1.EVEX.256.66.0F38.W1 59 /rVPBROADCASTQ ymm1 {k1}{z}, xmm2/m64BV/VAVX512VLAVX512FBroadcast a qword element in source operand to locations in ymm1 subject to writemask k1.EVEX.512.66.0F38.W1 59 /rVPBROADCASTQ zmm1 {k1}{z}, xmm2/m64BV/VAVX512FBroadcast a qword element in source operand to locations in zmm1 subject to writemask k1.EVEX.128.66.0F38.W0 59 /rVBROADCASTI32x2 xmm1 {k1}{z}, xmm2/m64CV/VAVX512VLAVX512DQBroadcast two dword elements in source operand to locations in xmm1 subject to writemask k1.

image/svg+xmlInstruction Operand EncodingDescriptionLoad integer data from the source operand (the second operand) and broadcast to all elements of the destination operand (the first operand).VEX256-encoded VPBROADCASTB/W/D/Q: The source operand is 8-bit, 16-bit, 32-bit, 64-bit memory location or the low 8-bit, 16-bit 32-bit, 64-bit data in an XMM register. The destination operand is a YMM register. VPBROADCASTI128 support the source operand of 128-bit memory location. Register source encodings for VPBROADCASTI128 is reserved and will #UD. Bits (MAXVL-1:256) of the destination register are zeroed.EVEX-encoded VPBROADCASTD/Q: The source operand is a 32-bit, 64-bit memory location or the low 32-bit, 64-bit data in an XMM register. The destination operand is a ZMM/YMM/XMM register and updated according to the writemask k1. VPBROADCASTI32X4 and VPBROADCASTI64X4: The destination operand is a ZMM register and updated according to the writemask k1. The source operand is 128-bit or 256-bit memory location. Register source encodings for VBROADCASTI32X4 and VBROADCASTI64X4 are reserved and will #UD.EVEX.256.66.0F38.W0 59 /rVBROADCASTI32x2 ymm1 {k1}{z}, xmm2/m64CV/VAVX512VLAVX512DQBroadcast two dword elements in source operand to locations in ymm1 subject to writemask k1.EVEX.512.66.0F38.W0 59 /rVBROADCASTI32x2 zmm1 {k1}{z}, xmm2/m64CV/VAVX512DQBroadcast two dword elements in source operand to locations in zmm1 subject to writemask k1.VEX.256.66.0F38.W0 5A /rVBROADCASTI128 ymm1, m128AV/VAVX2Broadcast 128 bits of integer data in mem to low and high 128-bits in ymm1.EVEX.256.66.0F38.W0 5A /rVBROADCASTI32X4 ymm1 {k1}{z}, m128DV/VAVX512VLAVX512FBroadcast 128 bits of 4 doubleword integer data in mem to locations in ymm1 using writemask k1.EVEX.512.66.0F38.W0 5A /rVBROADCASTI32X4 zmm1 {k1}{z}, m128DV/VAVX512FBroadcast 128 bits of 4 doubleword integer data in mem to locations in zmm1 using writemask k1.EVEX.256.66.0F38.W1 5A /rVBROADCASTI64X2 ymm1 {k1}{z}, m128CV/VAVX512VLAVX512DQBroadcast 128 bits of 2 quadword integer data in mem to locations in ymm1 using writemask k1.EVEX.512.66.0F38.W1 5A /rVBROADCASTI64X2 zmm1 {k1}{z}, m128CV/VAVX512DQBroadcast 128 bits of 2 quadword integer data in mem to locations in zmm1 using writemask k1.EVEX.512.66.0F38.W0 5B /rVBROADCASTI32X8 zmm1 {k1}{z}, m256EV/VAVX512DQBroadcast 256 bits of 8 doubleword integer data in mem to locations in zmm1 using writemask k1.EVEX.512.66.0F38.W1 5B /rVBROADCASTI64X4 zmm1 {k1}{z}, m256DV/VAVX512FBroadcast 256 bits of 4 quadword integer data in mem to locations in zmm1 using writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)NANABTuple1 ScalarModRM:reg (w)ModRM:r/m (r)NANACTuple2ModRM:reg (w)ModRM:r/m (r)NANADTuple4ModRM:reg (w)ModRM:r/m (r)NANAETuple8ModRM:reg (w)ModRM:r/m (r)NANAOpcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescription

image/svg+xmlNote: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.If VPBROADCASTI128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will cause an #UD exception.Figure 5-16. VPBROADCASTD Operation (VEX.256 encoded version)Figure 5-17. VPBROADCASTD Operation (128-bit version)Figure 5-18. VPBROADCASTQ Operation (256-bit version)DESTm32X0X0X0X0X0X0X0X0X0DESTm32X0X0X0X00X0000DESTm64X0X0X0X0X0

image/svg+xmlOperationVPBROADCASTB (EVEX encoded versions)(KL, VL) = (16, 128), (32, 256), (64, 512)FOR j := 0 TO KL-1i := j * 8IF k1[j] OR *no writemask*THEN DEST[i+7:i] := SRC[7:0]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+7:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+7:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0Figure 5-19. VBROADCASTI128 Operation (256-bit version)Figure 5-20. VBROADCASTI256 Operation (512-bit version)DESTm128X0X0X0DESTm256X0X0X0

image/svg+xmlVPBROADCASTW (EVEX encoded versions)(KL, VL) = (8, 128), (16, 256), (32, 512)FOR j := 0 TO KL-1i := j * 16IF k1[j] OR *no writemask*THEN DEST[i+15:i] := SRC[15:0]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+15:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+15:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0VPBROADCASTD (128 bit version)temp := SRC[31:0]DEST[31:0] := tempDEST[63:32] := tempDEST[95:64] := tempDEST[127:96] := tempDEST[MAXVL-1:128] := 0VPBROADCASTD (VEX.256 encoded version)temp := SRC[31:0]DEST[31:0] := tempDEST[63:32] := tempDEST[95:64] := tempDEST[127:96] := tempDEST[159:128] := tempDEST[191:160] := tempDEST[223:192] := tempDEST[255:224] := tempDEST[MAXVL-1:256] := 0VPBROADCASTD (EVEX encoded versions)(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask*THEN DEST[i+31:i] := SRC[31:0]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0

image/svg+xmlVPBROADCASTQ (VEX.256 encoded version)temp := SRC[63:0]DEST[63:0] := tempDEST[127:64] := tempDEST[191:128] := tempDEST[255:192] := tempDEST[MAXVL-1:256] := 0VPBROADCASTQ (EVEX encoded versions)(KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask*THEN DEST[i+63:i] := SRC[63:0]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+63:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0VBROADCASTI32x2 (EVEX encoded versions)(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32n := (j mod 2) * 32IF k1[j] OR *no writemask*THEN DEST[i+31:i] := SRC[n+31:n]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0VBROADCASTI128 (VEX.256 encoded version)temp := SRC[127:0]DEST[127:0] := tempDEST[255:128] := tempDEST[MAXVL-1:256] := 0

image/svg+xmlVBROADCASTI32X4 (EVEX encoded versions)(KL, VL) = (8, 256), (16, 512)FOR j := 0 TO KL-1i := j* 32n := (j modulo 4) * 32IF k1[j] OR *no writemask*THEN DEST[i+31:i] := SRC[n+31:n]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0VBROADCASTI64X2 (EVEX encoded versions)(KL, VL) = (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 64n := (j modulo 2) * 64IF k1[j] OR *no writemask*THEN DEST[i+63:i] := SRC[n+63:n]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+63:i] = 0FIFI;ENDFOR;VBROADCASTI32X8 (EVEX.U1.512 encoded version)FOR j := 0 TO 15i := j * 32n := (j modulo 8) * 32IF k1[j] OR *no writemask*THEN DEST[i+31:i] := SRC[n+31:n]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0

image/svg+xmlVBROADCASTI64X4 (EVEX.512 encoded version)FOR j := 0 TO 7i := j * 64n := (j modulo 4) * 64IF k1[j] OR *no writemask*THEN DEST[i+63:i] := SRC[n+63:n]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+63:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0Intel C/C++ Compiler Intrinsic EquivalentVPBROADCASTB __m512i _mm512_broadcastb_epi8( __m128i a);VPBROADCASTB __m512i _mm512_mask_broadcastb_epi8(__m512i s, __mmask64 k, __m128i a);VPBROADCASTB __m512i _mm512_maskz_broadcastb_epi8( __mmask64 k, __m128i a);VPBROADCASTB __m256i _mm256_broadcastb_epi8(__m128i a);VPBROADCASTB __m256i _mm256_mask_broadcastb_epi8(__m256i s, __mmask32 k, __m128i a);VPBROADCASTB __m256i _mm256_maskz_broadcastb_epi8( __mmask32 k, __m128i a);VPBROADCASTB __m128i _mm_mask_broadcastb_epi8(__m128i s, __mmask16 k, __m128i a);VPBROADCASTB __m128i _mm_maskz_broadcastb_epi8( __mmask16 k, __m128i a);VPBROADCASTB __m128i _mm_broadcastb_epi8(__m128i a);VPBROADCASTD __m512i _mm512_broadcastd_epi32( __m128i a);VPBROADCASTD __m512i _mm512_mask_broadcastd_epi32(__m512i s, __mmask16 k, __m128i a);VPBROADCASTD __m512i _mm512_maskz_broadcastd_epi32( __mmask16 k, __m128i a);VPBROADCASTD __m256i _mm256_broadcastd_epi32( __m128i a);VPBROADCASTD __m256i _mm256_mask_broadcastd_epi32(__m256i s, __mmask8 k, __m128i a);VPBROADCASTD __m256i _mm256_maskz_broadcastd_epi32( __mmask8 k, __m128i a);VPBROADCASTD __m128i _mm_broadcastd_epi32(__m128i a);VPBROADCASTD __m128i _mm_mask_broadcastd_epi32(__m128i s, __mmask8 k, __m128i a);VPBROADCASTD __m128i _mm_maskz_broadcastd_epi32( __mmask8 k, __m128i a);VPBROADCASTQ __m512i _mm512_broadcastq_epi64( __m128i a);VPBROADCASTQ __m512i _mm512_mask_broadcastq_epi64(__m512i s, __mmask8 k, __m128i a);VPBROADCASTQ __m512i _mm512_maskz_broadcastq_epi64( __mmask8 k, __m128i a);VPBROADCASTQ __m256i _mm256_broadcastq_epi64(__m128i a);VPBROADCASTQ __m256i _mm256_mask_broadcastq_epi64(__m256i s, __mmask8 k, __m128i a);VPBROADCASTQ __m256i _mm256_maskz_broadcastq_epi64( __mmask8 k, __m128i a);VPBROADCASTQ __m128i _mm_broadcastq_epi64(__m128i a);VPBROADCASTQ __m128i _mm_mask_broadcastq_epi64(__m128i s, __mmask8 k, __m128i a);VPBROADCASTQ __m128i _mm_maskz_broadcastq_epi64( __mmask8 k, __m128i a);VPBROADCASTW __m512i _mm512_broadcastw_epi16(__m128i a);VPBROADCASTW __m512i _mm512_mask_broadcastw_epi16(__m512i s, __mmask32 k, __m128i a);VPBROADCASTW __m512i _mm512_maskz_broadcastw_epi16( __mmask32 k, __m128i a);VPBROADCASTW __m256i _mm256_broadcastw_epi16(__m128i a);VPBROADCASTW __m256i _mm256_mask_broadcastw_epi16(__m256i s, __mmask16 k, __m128i a);VPBROADCASTW __m256i _mm256_maskz_broadcastw_epi16( __mmask16 k, __m128i a);VPBROADCASTW __m128i _mm_broadcastw_epi16(__m128i a);VPBROADCASTW __m128i _mm_mask_broadcastw_epi16(__m128i s, __mmask8 k, __m128i a);VPBROADCASTW __m128i _mm_maskz_broadcastw_epi16( __mmask8 k, __m128i a);VBROADCASTI32x2 __m512i _mm512_broadcast_i32x2( __m128i a);

image/svg+xmlVBROADCASTI32x2 __m512i _mm512_mask_broadcast_i32x2(__m512i s, __mmask16 k, __m128i a);VBROADCASTI32x2 __m512i _mm512_maskz_broadcast_i32x2( __mmask16 k, __m128i a);VBROADCASTI32x2 __m256i _mm256_broadcast_i32x2( __m128i a);VBROADCASTI32x2 __m256i _mm256_mask_broadcast_i32x2(__m256i s, __mmask8 k, __m128i a);VBROADCASTI32x2 __m256i _mm256_maskz_broadcast_i32x2( __mmask8 k, __m128i a);VBROADCASTI32x2 __m128i _mm_broadcast_i32x2(__m128i a);VBROADCASTI32x2 __m128i _mm_mask_broadcast_i32x2(__m128i s, __mmask8 k, __m128i a);VBROADCASTI32x2 __m128i _mm_maskz_broadcast_i32x2( __mmask8 k, __m128i a);VBROADCASTI32x4 __m512i _mm512_broadcast_i32x4( __m128i a);VBROADCASTI32x4 __m512i _mm512_mask_broadcast_i32x4(__m512i s, __mmask16 k, __m128i a);VBROADCASTI32x4 __m512i _mm512_maskz_broadcast_i32x4( __mmask16 k, __m128i a);VBROADCASTI32x4 __m256i _mm256_broadcast_i32x4( __m128i a);VBROADCASTI32x4 __m256i _mm256_mask_broadcast_i32x4(__m256i s, __mmask8 k, __m128i a);VBROADCASTI32x4 __m256i _mm256_maskz_broadcast_i32x4( __mmask8 k, __m128i a);VBROADCASTI32x8 __m512i _mm512_broadcast_i32x8( __m256i a);VBROADCASTI32x8 __m512i _mm512_mask_broadcast_i32x8(__m512i s, __mmask16 k, __m256i a);VBROADCASTI32x8 __m512i _mm512_maskz_broadcast_i32x8( __mmask16 k, __m256i a);VBROADCASTI64x2 __m512i _mm512_broadcast_i64x2( __m128i a);VBROADCASTI64x2 __m512i _mm512_mask_broadcast_i64x2(__m512i s, __mmask8 k, __m128i a);VBROADCASTI64x2 __m512i _mm512_maskz_broadcast_i64x2( __mmask8 k, __m128i a);VBROADCASTI64x2 __m256i _mm256_broadcast_i64x2( __m128i a);VBROADCASTI64x2 __m256i _mm256_mask_broadcast_i64x2(__m256i s, __mmask8 k, __m128i a);VBROADCASTI64x2 __m256i _mm256_maskz_broadcast_i64x2( __mmask8 k, __m128i a);VBROADCASTI64x4 __m512i _mm512_broadcast_i64x4( __m256i a);VBROADCASTI64x4 __m512i _mm512_mask_broadcast_i64x4(__m512i s, __mmask8 k, __m256i a);VBROADCASTI64x4 __m512i _mm512_maskz_broadcast_i64x4( __mmask8 k, __m256i a);SIMD Floating-Point ExceptionsNoneOther ExceptionsEVEX-encoded instructions, see Table2-23, “Type 6 Class Exception Conditions”. EVEX-encoded instructions, syntax with reg/mem operand, see Table2-53, “Type E6 Class Exception Conditions”.Additionally:#UDIf VEX.L = 0 for VPBROADCASTQ, VPBROADCASTI128.If EVEX.L’L = 0 for VBROADCASTI32X4/VBROADCASTI64X2.If EVEX.L’L < 10b for VBROADCASTI32X8/VBROADCASTI64X4.

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.