image/svg+xmlVPBLENDMB/VPBLENDMW—Blend Byte/Word Vectors Using an Opmask ControlInstruction Operand EncodingDescriptionPerforms an element-by-element blending of byte/word elements between the first source operand byte vector register and the second source operand byte vector from memory or register, using the instruction mask as selector. The result is written into the destination byte vector register.The destination and first source operands are ZMM/YMM/XMM registers. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit memory location.The mask is not used as a writemask for this instruction. Instead, the mask is used as an element selector: every element of the destination is conditionally selected between first source or second source using the value of the related mask bit (0 for first source, 1 for second source).Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.128.66.0F38.W0 66 /rVPBLENDMB xmm1 {k1}{z}, xmm2, xmm3/m128AV/VAVX512VLAVX512BWBlend byte integer vector xmm2 and byte vector xmm3/m128 and store the result in xmm1, under control mask.EVEX.256.66.0F38.W0 66 /r VPBLENDMB ymm1 {k1}{z}, ymm2, ymm3/m256AV/VAVX512VLAVX512BWBlend byte integer vector ymm2 and byte vector ymm3/m256 and store the result in ymm1, under control mask.EVEX.512.66.0F38.W0 66 /rVPBLENDMB zmm1 {k1}{z}, zmm2, zmm3/m512AV/VAVX512BWBlend byte integer vector zmm2 and byte vector zmm3/m512 and store the result in zmm1, under control mask.EVEX.128.66.0F38.W1 66 /rVPBLENDMW xmm1 {k1}{z}, xmm2, xmm3/m128AV/VAVX512VLAVX512BWBlend word integer vector xmm2 and word vector xmm3/m128 and store the result in xmm1, under control mask.EVEX.256.66.0F38.W1 66 /rVPBLENDMW ymm1 {k1}{z}, ymm2, ymm3/m256AV/VAVX512VLAVX512BWBlend word integer vector ymm2 and word vector ymm3/m256 and store the result in ymm1, under control mask.EVEX.512.66.0F38.W1 66 /rVPBLENDMW zmm1 {k1}{z}, zmm2, zmm3/m512AV/VAVX512BWBlend word integer vector zmm2 and word vector zmm3/m512 and store the result in zmm1, under control mask.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4AFull MemModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlOperationVPBLENDMB (EVEX encoded versions)(KL, VL) = (16, 128), (32, 256), (64, 512)FOR j := 0 TO KL-1i := j * 8IF k1[j] OR *no writemask*THEN DEST[i+7:i] := SRC2[i+7:i]ELSE IF *merging-masking*; merging-maskingTHEN DEST[i+7:i] := SRC1[i+7:i]ELSE ; zeroing-maskingDEST[i+7:i] := 0FI;FI;ENDFORDEST[MAXVL-1:VL] := 0;VPBLENDMW (EVEX encoded versions)(KL, VL) = (8, 128), (16, 256), (32, 512)FOR j := 0 TO KL-1i := j * 16IF k1[j] OR *no writemask*THEN DEST[i+15:i] := SRC2[i+15:i]ELSE IF *merging-masking*; merging-maskingTHEN DEST[i+15:i] := SRC1[i+15:i]ELSE ; zeroing-maskingDEST[i+15:i] := 0FI;FI;ENDFORDEST[MAXVL-1:VL] := 0Intel C/C++ Compiler Intrinsic EquivalentVPBLENDMB __m512i _mm512_mask_blend_epi8(__mmask64 m, __m512i a, __m512i b);VPBLENDMB __m256i _mm256_mask_blend_epi8(__mmask32 m, __m256i a, __m256i b);VPBLENDMB __m128i _mm_mask_blend_epi8(__mmask16 m, __m128i a, __m128i b);VPBLENDMW __m512i _mm512_mask_blend_epi16(__mmask32 m, __m512i a, __m512i b);VPBLENDMW __m256i _mm256_mask_blend_epi16(__mmask16 m, __m256i a, __m256i b);VPBLENDMW __m128i _mm_mask_blend_epi16(__mmask8 m, __m128i a, __m128i b);SIMD Floating-Point ExceptionsNoneOther ExceptionsSee Table2-49, “Type E4 Class Exception Conditions”.

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