VP4DPWSSD — Dot Product of Signed Words with Dword Accumulation (4-iterations)Instruction Operand EncodingDescriptionThis instruction computes 4 sequential register source-block dot-products of two signed word operands with doubleword accumulation; see Figure7-1 below. The memory operand is sequentially selected in each of the four steps.In the above box, the notation of “+3”' is used to denote that the instruction accesses 4 source registers based on that operand; sources are consecutive, start in a multiple of 4 boundary, and contain the encoded register operand.This instruction supports memory fault suppression. The entire memory operand is loaded if any bit of the lowest 16-bits of the mask is set to 1 or if a “no masking” encoding is used.The tuple type Tuple1_4X implies that four 32-bit elements (16 bytes) are referenced by the memory operation portion of this instruction.Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.512.F2.0F38.W0 52 /rVP4DPWSSD zmm1{k1}{z}, zmm2+3, m128AV/VAVX512_4VNNIWMultiply signed words from source register block indicated by zmm2 by signed words from m128 and accumulate resulting signed dwords in zmm1.Op/EnTupleOperand 1Operand 2Operand 3Operand 4ATuple1_4XModRM:reg (r, w)EVEX.vvvv (r)ModRM:r/m (r)NAFigure 7-1. Register Source-Block Dot Product of Two Signed Word Operands with Doubleword Accumulation1NOTES:1. For illustration purposes, one source-block dot product instance is shown out ofthe four.b1b0b1b0c1c0c1=c1+a2*b0+a3*b1c0=c0+a0*b0+a1*b1a3a2a1a016b16b16b16b32b32b32b32b
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