image/svg+xml VGETMANTSD—Extract Float64 of Normalized Mantissas from Float64 Scalar Instruction Operand Encoding Description Convert the double-precision floating values in the low quadword element of the second source operand (the third operand) to DP FP value with the mantissa normalization and sign control specified by the imm8 byte, see Figure5-15 . The converted result is written to the low quadword element of the destination operand (the first operand) using writemask k1. Bits (127:64) of the XMM register destination are copied from corresponding bits in the first source operand. The normalized mantissa is specified by interv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte. The conversion operation is: GetMant ( x ) = ± 2 k |x.significand| where: 1 < = |x.significand| < 2 Unbiased exponent k can be either 0 or -1, depending on the interval range defined by interv, the range of the significand and whether the exponent of the source is even or odd. The sign of the final result is determined by sc and the source sign. The encoded value of imm8[1:0] and sign control are shown in Figure5-15. The converted DP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a mantissa normalized to the range specified by interv. The GetMant() function follows Table 5-7 when dealing with floating-point special numbers. If writemasking is used, the low quadword element of the destination operand is conditionally updated depending on the value of writemask register k1. If writemasking is not used, the low quadword element of the destination operand is unconditionally updated. Opcode/ Instruction Op/ En 64/32 bit Mode Support CPUID Feature Flag Description EVEX.LLIG.66.0F3A.W1 27 /r ib VGETMANTSD xmm1 {k1}{z}, xmm2, xmm3/m64{sae}, imm8 AV/VAVX512FExtract the normalized mantissa of the low float64 element in xmm3/m64 using imm 8 for sign control and mantissa interval normalization. Store the mantissa to xmm1 under the writemask k1 and merge with the other elements of xmm2. Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4 ATuple1 ScalarModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA image/svg+xml Operation // getmant_fp64(src, sign_control, normalization_interval) is defined in the operation section of VGETMANTPD VGETMANTSD (EVEX encoded version) SignCtrl[1:0] := IMM8[3:2]; Interv[1:0] := IMM8[1:0]; IF k1[0] OR *no writemask* THEN DEST[63:0] := getmant_fp64(src, sign_control, normalization_interval) ELSE IF *merging-masking*; merging-masking THEN *DEST[63:0] remains unchanged* ELSE ; zeroing-masking DEST[63:0] := 0 FI FI; DEST[127:64] := SRC1[127:64] DEST[MAXVL-1:128] := 0 Intel C/C++ Compiler Intrinsic Equivalent VGETMANTSD __m128d _mm_getmant_sd( __m128d a, __m128 b, enum intv, enum sgn); VGETMANTSD __m128d _mm_mask_getmant_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn); VGETMANTSD __m128d _mm_maskz_getmant_sd( __mmask8 k, __m128 a, __m128d b, enum intv, enum sgn); VGETMANTSD __m128d _mm_getmant_round_sd( __m128d a, __m128 b, enum intv, enum sgn, int r); VGETMANTSD __m128d _mm_mask_getmant_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn, int r); VGETMANTSD __m128d _mm_maskz_getmant_round_sd( __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn, int r); SIMD Floating-Point Exceptions Denormal, Invalid Other Exceptions See Table2-47, “Type E3 Class Exception Conditions”. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .