image/svg+xml VGETMANTPS—Extract Float32 Vector of Normalized Mantissas from Float32 Vector Instruction Operand Encoding Description Convert single-precision floating values in the source operand (the second operand) to SP FP values with the mantissa normalization and sign control specified by the imm8 byte, see Figure5-15. The converted results are written to the destination operand (the first operand) using writemask k1. The normalized mantissa is specified by interv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte. The destination operand is a ZMM/YMM/XMM register updated under the writemask. The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32- bit memory location. For each input SP FP value x, The conversion operation is: GetMant ( x ) = ± 2 k |x.significand| where: 1 < = |x.significand| < 2 Unbiased exponent k can be either 0 or -1, depending on the interval range defined by interv, the range of the significand and whether the exponent of the source is even or odd. The sign of the final result is determined by sc and the source sign. The encoded value of imm8[1:0] and sign control are shown in Figure5-15. Each converted SP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a mantissa normalized to the range specified by interv. The GetMant() function follows Table 5-7 when dealing with floating-point special numbers. This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1 are computed and stored into the destination. Elements in zmm1 with the corresponding bit clear in k1 retain their previous values. Note: EVEX.vvvv is reserved and must be 1111b, VEX.L must be 0; otherwise instructions will #UD. Opcode/ Instruction Op/ En 64/32 bit Mode Support CPUID Feature Flag Description EVEX.128.66.0F3A.W0 26 /r ib VGETMANTPS xmm1 {k1}{z}, xmm2/m128/m32bcst, imm8 AV/VAVX512VL AVX512F Get normalized mantissa from float32 vector xmm2/m128/m32bcst and store the result in xmm1, using imm8 for sign control and mantissa interval normalization, under writemask. EVEX.256.66.0F3A.W0 26 /r ib VGETMANTPS ymm1 {k1}{z}, ymm2/m256/m32bcst, imm8 AV/VAVX512VL AVX512F Get normalized mantissa from float32 vector ymm2/m256/m32bcst and store the result in ymm1, using imm8 for sign control and mantissa interval normalization, under writemask. EVEX.512.66.0F3A.W0 26 /r ib VGETMANTPS zmm1 {k1}{z}, zmm2/m512/m32bcst{sae}, imm8 AV/VAVX512FGet normalized mantissa from float32 vector zmm2/m512/m32bcst and store the result in zmm1, using imm8 for sign control and mantissa interval normalization, under writemask. Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4 AFullModRM:reg (w)ModRM:r/m (r)Imm8NA image/svg+xml Operation def getmant_fp32(src, sign_control, normalization_interval): bias := 127 dst.sign := sign_control[0] ? 0 : src.sign signed_one := sign_control[0] ? +1.0 : -1.0 dst.exp := src.exp dst.fraction := src.fraction zero := (dst.exp = 0) and ((dst.fraction = 0) or (MXCSR.DAZ=1)) denormal := (dst.exp = 0) and (dst.fraction != 0) and (MXCSR.DAZ=0) infinity := (dst.exp = 0xFF) and (dst.fraction = 0) nan := (dst.exp = 0xFF) and (dst.fraction != 0) src_signaling := src.fraction[22] snan := nan and (src_signaling = 0) positive := (src.sign = 0) negative := (src.sign = 1) if nan: if snan: MXCSR.IE := 1 return qnan(src) if positive and (zero or infinity): return 1.0 if negative: if zero: return signed_one if infinity: if sign_control[1]: MXCSR.IE := 1 return QNaN_Indefinite return signed_one if sign_control[1]: MXCSR.IE := 1 return QNaN_Indefinite if denormal: jbit := 0 dst.exp := bias while jbit = 0: jbit := dst.fraction[22] dst.fraction := dst.fraction << 1 dst.exp : = dst.exp - 1 MXCSR.DE := 1 unbiased_exp := dst.exp - bias odd_exp := unbiased_exp[0] signaling_bit := dst.fraction[22] if normalization_interval = 0b00: dst.exp := bias else if normalization_interval = 0b01: dst.exp := odd_exp ? bias-1 : bias else if normalization_interval = 0b10: dst.exp := bias-1 else if normalization_interval = 0b11: dst.exp := signaling_bit ? bias-1 : bias image/svg+xml return dst VGETMANTPS (EVEX encoded versions) VGETMANTPS dest{k1}, src, imm8 VL = 128, 256, or 512 KL := VL / 32 sign_control := imm8[3:2] normalization_interval := imm8[1:0] FOR i := 0 to KL-1: IF k1[i] or *no writemask*: IF SRC is memory and (EVEX.b = 1): tsrc := src.float[0] ELSE: tsrc := src.float[i] DEST.float[i] := getmant_fp32(tsrc, sign_control, normalization_interval) ELSE IF *zeroing*: DEST.float[i] := 0 //else DEST.float[i] remains unchanged DEST[MAX_VL-1:VL] := 0 Intel C/C++ Compiler Intrinsic Equivalent VGETMANTPS __m512 _mm512_getmant_ps( __m512 a, enum intv, enum sgn); VGETMANTPS __m512 _mm512_mask_getmant_ps(__m512 s, __mmask16 k, __m512 a, enum intv, enum sgn; VGETMANTPS __m512 _mm512_maskz_getmant_ps(__mmask16 k, __m512 a, enum intv, enum sgn); VGETMANTPS __m512 _mm512_getmant_round_ps( __m512 a, enum intv, enum sgn, int r); VGETMANTPS __m512 _mm512_mask_getmant_round_ps(__m512 s, __mmask16 k, __m512 a, enum intv, enum sgn, int r); VGETMANTPS __m512 _mm512_maskz_getmant_round_ps(__mmask16 k, __m512 a, enum intv, enum sgn, int r); VGETMANTPS __m256 _mm256_getmant_ps( __m256 a, enum intv, enum sgn); VGETMANTPS __m256 _mm256_mask_getmant_ps(__m256 s, __mmask8 k, __m256 a, enum intv, enum sgn); VGETMANTPS __m256 _mm256_maskz_getmant_ps( __mmask8 k, __m256 a, enum intv, enum sgn); VGETMANTPS __m128 _mm_getmant_ps( __m128 a, enum intv, enum sgn); VGETMANTPS __m128 _mm_mask_getmant_ps(__m128 s, __mmask8 k, __m128 a, enum intv, enum sgn); VGETMANTPS __m128 _mm_maskz_getmant_ps( __mmask8 k, __m128 a, enum intv, enum sgn); SIMD Floating-Point Exceptions Denormal, Invalid Other Exceptions See Table2-46, “Type E2 Class Exception Conditions”; additionally: #UD If EVEX.vvvv != 1111B. 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