image/svg+xml VGETEXPSS—Convert Exponents of Scalar SP FP Values to SP FP Value Instruction Operand Encoding Description Extracts the biased exponent from the normalized SP FP representation of the low doubleword data element of the source operand (the third operand) as unbiased signed integer value, or convert the denormal representation of input data to unbiased negative integer values. The integer value of the unbiased exponent is converted to single- precision FP value and written to the destination operand (the first operand) as SP FP numbers. Bits (127:32) of the XMM register destination are copied from corresponding bits in the first source operand. The destination must be a XMM register, the source operand can be a XMM register or a float32 memory location. If writemasking is used, the low doubleword element of the destination operand is conditionally updated depending on the value of writemask register k1. If writemasking is not used, the low doubleword element of the destination operand is unconditionally updated. Each GETEXP operation converts the exponent value into a FP number (permitting input value in denormal repre- sentation). Special cases of input values are listed in Table 5-6. The formula is: GETEXP(x) = floor(log 2 (|x|)) Notation floor(x) stands for maximal integer not exceeding real number x. Software usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation and GETMANT operation (see VGETMANTPD). Thus VGETEXPxx instruction do not require software to handle SIMD FP exceptions. Operation // NormalizeExpTinySPFP(SRC[31:0]) is defined in the Operation section of VGETEXPPS // ConvertExpSPFP(SRC[31:0]) is defined in the Operation section of VGETEXPPS VGETEXPSS (EVEX encoded version) IF k1[0] OR *no writemask* THEN DEST[31:0] := ConvertExpDPFP(SRC2[31:0]) ELSE IF *merging-masking*; merging-masking THEN *DEST[31:0] remains unchanged* ELSE ; zeroing-masking DEST[31:0]:= 0 FI FI; ENDFOR DEST[127:32] := SRC1[127:32] DEST[MAXVL-1:128] := 0 Opcode/ Instruction Op/ En 64/32 bit Mode Support CPUID Feature Flag Description EVEX.LLIG.66.0F38.W0 43 /r VGETEXPSS xmm1 {k1}{z}, xmm2, xmm3/m32{sae} AV/VAVX512FConvert the biased exponent (bits 30:23) of the low single- precision floating-point value in xmm3/m32 to a SP FP value representing unbiased integer exponent. Stores the result to xmm1 under the writemask k1 and merge with the other elements of xmm2. Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4 ATuple1 ScalarModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA image/svg+xml Intel C/C++ Compiler Intrinsic Equivalent VGETEXPSS __m128 _mm_getexp_ss( __m128 a, __m128 b); VGETEXPSS __m128 _mm_mask_getexp_ss(__m128 s, __mmask8 k, __m128 a, __m128 b); VGETEXPSS __m128 _mm_maskz_getexp_ss( __mmask8 k, __m128 a, __m128 b); VGETEXPSS __m128 _mm_getexp_round_ss( __m128 a, __m128 b, int sae); VGETEXPSS __m128 _mm_mask_getexp_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int sae); VGETEXPSS __m128 _mm_maskz_getexp_round_ss( __mmask8 k, __m128 a, __m128 b, int sae); SIMD Floating-Point Exceptions Invalid, Denormal Other Exceptions See Table2-47, “Type E3 Class Exception Conditions”. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .