image/svg+xmlVGETEXPPS—Convert Exponents of Packed SP FP Values to SP FP ValuesInstruction Operand EncodingDescriptionExtracts the biased exponents from the normalized SP FP representation of each dword element of the source operand (the second operand) as unbiased signed integer value, or convert the denormal representation of input data to unbiased negative integer values. Each integer value of the unbiased exponent is converted to single-preci-sion FP value and written to the corresponding dword elements of the destination operand (the first operand) as SP FP numbers. The destination operand is a ZMM/YMM/XMM register and updated under the writemask. The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-bit memory location.EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.Each GETEXP operation converts the exponent value into a FP number (permitting input value in denormal repre-sentation). Special cases of input values are listed in Table 5-6.The formula is:GETEXP(x) = floor(log2(|x|)) Notation floor(x) stands for maximal integer not exceeding real number x. Software usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation and GETMANT operation (see VGETMANTPD). Thus VGETEXPxx instruction do not require software to handle SIMD FP exceptions.Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.128.66.0F38.W0 42 /rVGETEXPPS xmm1 {k1}{z}, xmm2/m128/m32bcstAV/VAVX512VLAVX512FConvert the exponent of packed single-precision floating-point values in the source operand to SP FP results representing unbiased integer exponents and stores the results in the destination register.EVEX.256.66.0F38.W0 42 /rVGETEXPPS ymm1 {k1}{z}, ymm2/m256/m32bcstAV/VAVX512VLAVX512FConvert the exponent of packed single-precision floating-point values in the source operand to SP FP results representing unbiased integer exponents and stores the results in the destination register.EVEX.512.66.0F38.W0 42 /rVGETEXPPS zmm1 {k1}{z}, zmm2/m512/m32bcst{sae}AV/VAVX512FConvert the exponent of packed single-precision floating-point values in the source operand to SP FP results representing unbiased integer exponents and stores the results in the destination register.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4AFullModRM:reg (w)ModRM:r/m (r)NANATable 5-6. VGETEXPPS/SS Special CasesInput OperandResultCommentssrc1 = NaNQNaN(src1)If (SRC = SNaN) then #IEIf (SRC = denormal) then #DE0 < |src1| < INFfloor(log2(|src1|)) | src1| = +INF+INF| src1| = 0-INF

image/svg+xmlFigure5-14 illustrates the VGETEXPPS functionality on input values with normalized representation.OperationNormalizeExpTinySPFP(SRC[31:0]){// Jbit is the hidden integral bit of a FP number. In case of denormal number it has the value of ZERO.Src.Jbit := 0;Dst.exp := 1; Dst.fraction := SRC[22:0];WHILE(Src.Jbit = 0){Src.Jbit := Dst.fraction[22];// Get the fraction MSBDst.fraction := Dst.fraction << 1;// One bit shift leftDst.exp--;// Decrement the exponent}Dst.fraction := 0;// zero out fraction bitsDst.sign := 1;// Return negative signTMP[31:0] := MXCSR.DAZ? 0 : (Dst.sign << 31) OR (Dst.exp << 23) OR (Dst.fraction);Return (TMP[31:0]);}ConvertExpSPFP(SRC[31:0]){Src.sign := 0;// Zero out sign bitSrc.exp := SRC[30:23];Src.fraction := SRC[22:0];// Check for NaNIF (SRC = NaN) {IF ( SRC = SNAN ) SET IE;Return QNAN(SRC);}// Check for +INFIF (Src = +INF) RETURN (Src);// check if zero operandIF ((Src.exp = 0) AND ((Src.fraction = 0) OR (MXCSR.DAZ = 1))) Return (-INF);}ELSE // check if denormal operand (notice that MXCSR.DAZ = 0){Figure 5-14. VGETEXPPS Functionality On Normal Input values313029282726252423222120191817161514131211109876543210sSrc = 2^101000000000000000000000000000000SAR Src, 23 = 080h00000000000000000000000010000000-Bias11111111111111111111111110000001Tmp - Bias = 100000000000000000000000000000001Cvt_PI2PS(01h) = 2^000111111100000000000000000000000expFraction

image/svg+xmlIF ((Src.exp = 0) AND (Src.fraction != 0)) {TMP[31:0] := NormalizeExpTinySPFP(SRC[31:0]);// Get Normalized ExponentSet #DE}ELSE// exponent value is correct{TMP[31:0] := (Src.sign << 31) OR (Src.exp << 23) OR (Src.fraction);}TMP := SAR(TMP, 23);// Shift Arithmetic RightTMP := TMP – 127;// Subtract BiasReturn CvtI2S(TMP);// Convert INT to Single-Precision FP number}}VGETEXPPS (EVEX encoded versions)(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask*THEN IF (EVEX.b = 1) AND (SRC *is memory*)THENDEST[i+31:i] :=ConvertExpSPFP(SRC[31:0])ELSE DEST[i+31:i] :=ConvertExpSPFP(SRC[i+31:i])FI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentVGETEXPPS __m512 _mm512_getexp_ps( __m512 a);VGETEXPPS __m512 _mm512_mask_getexp_ps(__m512 s, __mmask16 k, __m512 a);VGETEXPPS __m512 _mm512_maskz_getexp_ps( __mmask16 k, __m512 a);VGETEXPPS __m512 _mm512_getexp_round_ps( __m512 a, int sae);VGETEXPPS __m512 _mm512_mask_getexp_round_ps(__m512 s, __mmask16 k, __m512 a, int sae);VGETEXPPS __m512 _mm512_maskz_getexp_round_ps( __mmask16 k, __m512 a, int sae);VGETEXPPS __m256 _mm256_getexp_ps(__m256 a);VGETEXPPS __m256 _mm256_mask_getexp_ps(__m256 s, __mmask8 k, __m256 a);VGETEXPPS __m256 _mm256_maskz_getexp_ps( __mmask8 k, __m256 a);VGETEXPPS __m128 _mm_getexp_ps(__m128 a);VGETEXPPS __m128 _mm_mask_getexp_ps(__m128 s, __mmask8 k, __m128 a);VGETEXPPS __m128 _mm_maskz_getexp_ps( __mmask8 k, __m128 a);SIMD Floating-Point ExceptionsInvalid, DenormalOther ExceptionsSee Table2-46, “Type E2 Class Exception Conditions”; additionally:#UDIf EVEX.vvvv != 1111B.

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