image/svg+xmlVFPCLASSSD—Tests Types Of a Scalar Float64 ValuesInstruction Operand EncodingDescriptionThe FPCLASSSD instruction checks the low double precision floating point value in the source operand for special categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is classified against. The classified results of all specified categories of an input value are ORed together to form the final boolean result for the input element. The result is written to the low bit in a mask register k2 according to the writemask k1. Bits MAX_KL-1: 1 of the destination are cleared.The classification categories specified by imm8 are shown in Figure5-13. The classification test for each category is listed in Table 5-4.EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.OperationCheckFPClassDP (tsrc[63:0], imm8[7:0]){NegNum := tsrc[63];IF (tsrc[62:52]=07FFh) Then ExpAllOnes := 1; FI;IF (tsrc[62:52]=0h) Then ExpAllZeros := 1;IF (ExpAllZeros AND MXCSR.DAZ) Then MantAllZeros := 1;ELSIF (tsrc[51:0]=0h) ThenMantAllZeros := 1;FI;ZeroNumber := ExpAllZeros AND MantAllZerosSignalingBit := tsrc[51];sNaN_res := ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit); // sNaNqNaN_res := ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit; // qNaNPzero_res := NOT(NegNum) AND ExpAllZeros AND MantAllZeros; // +0Nzero_res := NegNum AND ExpAllZeros AND MantAllZeros; // -0PInf_res := NOT(NegNum) AND ExpAllOnes AND MantAllZeros; // +InfNInf_res := NegNum AND ExpAllOnes AND MantAllZeros; // -InfDenorm_res := ExpAllZeros AND NOT(MantAllZeros); // denormFinNeg_res := NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber); // -finitebResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res );Return bResult;} //* end of CheckFPClassDP() *//Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.LLIG.66.0F3A.W1 67 /r ibVFPCLASSSD k2 {k1}, xmm2/m64, imm8AV/VAVX512DQTests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result. Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ATuple1 ScalarModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlVFPCLASSSD (EVEX encoded version)IF k1[0] OR *no writemask*THEN DEST[0] := CheckFPClassDP(SRC1[63:0], imm8[7:0])ELSE DEST[0] := 0; zeroing-masking onlyFI;DEST[MAX_KL-1:1] := 0Intel C/C++ Compiler Intrinsic EquivalentVFPCLASSSD __mmask8 _mm_fpclass_sd_mask( __m128d a, int c)VFPCLASSSD __mmask8 _mm_mask_fpclass_sd_mask( __mmask8 m, __m128d a, int c)SIMD Floating-Point ExceptionsNoneOther ExceptionsSee Table2-53, “Type E6 Class Exception Conditions”; additionally:#UDIf EVEX.vvvv != 1111B.

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