image/svg+xmlVFPCLASSPD—Tests Types Of a Packed Float64 ValuesInstruction Operand EncodingDescriptionThe FPCLASSPD instruction checks the packed double precision floating point values for special categories, speci-fied by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is classified against. The classified results of all specified categories of an input value are ORed together to form the final boolean result for the input element. The result of each element is written to the corre-sponding bit in a mask register k2 according to the writemask k1. Bits [MAX_KL-1:8/4/2] of the destination are cleared.The classification categories specified by imm8 are shown in Figure5-13. The classification test for each category is listed in Table 5-4.The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location.EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.128.66.0F3A.W1 66 /r ibVFPCLASSPD k2 {k1}, xmm2/m128/m64bcst, imm8AV/VAVX512VLAVX512DQTests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.EVEX.256.66.0F3A.W1 66 /r ibVFPCLASSPD k2 {k1}, ymm2/m256/m64bcst, imm8AV/VAVX512VLAVX512DQTests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.EVEX.512.66.0F3A.W1 66 /r ibVFPCLASSPD k2 {k1}, zmm2/m512/m64bcst, imm8AV/VAVX512DQTests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4AFullModRM:reg (w)ModRM:r/m (r)NANAFigure 5-13. Imm8 Byte Specifier of Special Case FP Values for VFPCLASSPD/SD/PS/SSTable 5-4. Classifier Operations for VFPCLASSPD/SD/PS/SSBitsImm8[0]Imm8[1]Imm8[2]Imm8[3]Imm8[4]Imm8[5]Imm8[6]Imm8[7]CategoryQNANPosZeroNegZeroPosINFNegINFDenormalNegativeSNANClassifierChecks for QNaNChecks for +0Checks for -0Checks for +INFChecks for -INFChecks for DenormalChecks for Negative finiteChecks for SNaN70246531QNaNSNaNNeg. FiniteDenormalNeg. INF+INFNeg. 0+0

image/svg+xmlOperationCheckFPClassDP (tsrc[63:0], imm8[7:0]){//* Start checking the source operand for special type *//NegNum := tsrc[63];IF (tsrc[62:52]=07FFh) Then ExpAllOnes := 1; FI;IF (tsrc[62:52]=0h) Then ExpAllZeros := 1;IF (ExpAllZeros AND MXCSR.DAZ) Then MantAllZeros := 1;ELSIF (tsrc[51:0]=0h) ThenMantAllZeros := 1;FI;ZeroNumber := ExpAllZeros AND MantAllZerosSignalingBit := tsrc[51];sNaN_res := ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit); // sNaNqNaN_res := ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit; // qNaNPzero_res := NOT(NegNum) AND ExpAllZeros AND MantAllZeros; // +0Nzero_res := NegNum AND ExpAllZeros AND MantAllZeros; // -0PInf_res := NOT(NegNum) AND ExpAllOnes AND MantAllZeros; // +InfNInf_res := NegNum AND ExpAllOnes AND MantAllZeros; // -InfDenorm_res := ExpAllZeros AND NOT(MantAllZeros); // denormFinNeg_res := NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber); // -finitebResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res );Return bResult;} //* end of CheckFPClassDP() *//VFPCLASSPD (EVEX Encoded versions)(KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask*THEN IF (EVEX.b == 1) AND (SRC *is memory*)THENDEST[j] := CheckFPClassDP(SRC1[63:0], imm8[7:0]);ELSE DEST[j] := CheckFPClassDP(SRC1[i+63:i], imm8[7:0]);FI;ELSE DEST[j] := 0; zeroing-masking onlyFI;ENDFORDEST[MAX_KL-1:KL] := 0

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentVFPCLASSPD __mmask8 _mm512_fpclass_pd_mask( __m512d a, int c);VFPCLASSPD __mmask8 _mm512_mask_fpclass_pd_mask( __mmask8 m, __m512d a, int c)VFPCLASSPD __mmask8 _mm256_fpclass_pd_mask( __m256d a, int c)VFPCLASSPD __mmask8 _mm256_mask_fpclass_pd_mask( __mmask8 m, __m256d a, int c)VFPCLASSPD __mmask8 _mm_fpclass_pd_mask( __m128d a, int c)VFPCLASSPD __mmask8 _mm_mask_fpclass_pd_mask( __mmask8 m, __m128d a, int c)SIMD Floating-Point ExceptionsNoneOther ExceptionsSee Table2-49, “Type E4 Class Exception Conditions”; additionally:#UDIf EVEX.vvvv != 1111B.

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