image/svg+xmlVFIXUPIMMSD—Fix Up Special Scalar Float64 ValueInstruction Operand EncodingDescriptionPerform a fix-up of the low quadword element encoded in double-precision floating-point format in the first source operand (the second operand) using a 32-bit, two-level look-up table specified in the low quadword element of the second source operand (the third operand) with exception reporting specifier imm8. The element that is fixed-up is selected by mask bit of 1 specified in the opmask k1. Mask bit of 0 in the opmask k1 or table response action of 0000b preserves the corresponding element of the first operand. The fixed-up element from the first source operand or the preserved element in the first operand becomes the low quadword element of the destination operand (the first operand). Bits 127:64 of the destination operand is copied from the corresponding bits of the first source operand. The destination and first source operands are XMM registers. The second source operand can be a XMM register or a 64- bit memory location.The two-level look-up table perform a fix-up of each DP FP input data in the first source operand by decoding the input data encoding into 8 token types. A response table is defined for each token type that converts the input encoding in the first source operand with one of 16 response actions. This instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source so that they match the spec, although it is generally useful for fixing up the results of multiple-instruction sequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF according to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incor-rect result. To deal with this, VFIXUPIMMPD can be used after the N-R reciprocal sequence to set the result to the correct value (i.e. INF when the input is 0).If MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and do not trigger any fixup nor fault reporting.Imm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).MXCSR.DAZ is used and refer to zmm2 only (i.e. zmm1 is not considered as zero in case MXCSR.DAZ is set).MXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8 bits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.Operationenum TOKEN_TYPE{QNAN_TOKEN := 0,SNAN_TOKEN := 1,ZERO_VALUE_TOKEN := 2,POS_ONE_VALUE_TOKEN := 3,NEG_INF_TOKEN := 4,POS_INF_TOKEN := 5,NEG_VALUE_TOKEN := 6,POS_VALUE_TOKEN := 7}Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.LLIG.66.0F3A.W1 55 /r ibVFIXUPIMMSD xmm1 {k1}{z}, xmm2, xmm3/m64{sae}, imm8AV/VAVX512FFix up a float64 number in the low quadword element of xmm2 using scalar int32 table in xmm3/m64 and store the result in xmm1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ATuple1 ScalarModRM:reg (r, w)EVEX.vvvv (r)ModRM:r/m (r)Imm8

image/svg+xmlFIXUPIMM_DP (dest[63:0], src1[63:0],tbl3[63:0], imm8 [7:0]){tsrc[63:0] := ((src1[62:52] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[63:0]CASE(tsrc[63:0] of TOKEN_TYPE) {QNAN_TOKEN: j := 0;SNAN_TOKEN: j := 1;ZERO_VALUE_TOKEN: j := 2;POS_ONE_VALUE_TOKEN: j := 3;NEG_INF_TOKEN: j := 4;POS_INF_TOKEN: j := 5;NEG_VALUE_TOKEN: j := 6;POS_VALUE_TOKEN: j := 7;}; end source special CASE(tsrc…); The required response from src3 table is extractedtoken_response[3:0] = tbl3[3+4*j:4*j];CASE(token_response[3:0]) {0000: dest[63:0] := dest[63:0] ; preserve content of DEST0001: dest[63:0] := tsrc[63:0]; ; pass through src1 normal input value, denormal as zero0010: dest[63:0] := QNaN(tsrc[63:0]);0011: dest[63:0] := QNAN_Indefinite;0100:dest[63:0] := -INF;0101: dest[63:0] := +INF;0110: dest[63:0] := tsrc.sign? –INF : +INF;0111: dest[63:0] := -0;1000: dest[63:0] := +0;1001: dest[63:0] := -1;1010: dest[63:0] := +1;1011: dest[63:0] := ½;1100: dest[63:0] := 90.0;1101: dest[63:0] := PI/2;1110: dest[63:0] := MAX_FLOAT;1111: dest[63:0] := -MAX_FLOAT;} ; end of token_response CASE; The required fault reporting from imm8 is extracted; TOKENs are mutually exclusive and TOKENs priority defines the order.  ; Multiple faults related to a single token can occur simultaneously.IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE;IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE;IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE;IF (tsrc[63:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;IF (tsrc[63:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;IF (tsrc[63:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE;IF (tsrc[63:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;; end fault reporting return dest[63:0];} ; end of FIXUPIMM_DP()

image/svg+xmlVFIXUPIMMSD (EVEX encoded version)IF k1[0] OR *no writemask*THEN DEST[63:0] := FIXUPIMM_DP(DEST[63:0], SRC1[63:0], SRC2[63:0], imm8 [7:0])ELSE IF *merging-masking*; merging-maskingTHEN *DEST[63:0] remains unchanged*ELSE DEST[63:0] := 0; zeroing-maskingFIFI;DEST[127:64] := SRC1[127:64]DEST[MAXVL-1:128] := 0Immediate Control Description:Intel C/C++ Compiler Intrinsic EquivalentVFIXUPIMMSD __m128d _mm_fixupimm_sd( __m128d a, __m128i tbl, int imm);VFIXUPIMMSD __m128d _mm_mask_fixupimm_sd(__m128d s, __mmask8 k, __m128d a, __m128i tbl, int imm);VFIXUPIMMSD __m128d _mm_maskz_fixupimm_sd( __mmask8 k, __m128d a, __m128i tbl, int imm);VFIXUPIMMSD __m128d _mm_fixupimm_round_sd( __m128d a, __m128i tbl, int imm, int sae);VFIXUPIMMSD __m128d _mm_mask_fixupimm_round_sd(__m128d s, __mmask8 k, __m128d a, __m128i tbl, int imm, int sae);VFIXUPIMMSD __m128d _mm_maskz_fixupimm_round_sd( __mmask8 k, __m128d a, __m128i tbl, int imm, int sae);SIMD Floating-Point ExceptionsZero, InvalidOther ExceptionsSee Table2-47, “Type E3 Class Exception Conditions”.Figure 5-11. VFIXUPIMMSD Immediate Control Description76543210+INF #IE-INF #IESNaN #IE-VE #IEONE #IEONE #ZEZERO #IEZERO #ZE

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.