image/svg+xmlVEXP2PD—Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative ErrorInstruction Operand EncodingDescriptionComputes the approximate base-2 exponential evaluation of the double-precision floating-point values in the source operand (the second operand) and stores the results to the destination operand (the first operand) using the writemask k1. The approximate base-2 exponential is evaluated with less than 2^-23 of relative error. Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results are flushed to zeros and do not signal #UE, irrespective of MXCSR.FTZ.The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1. EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.A numerically exact implementation of VEXP2xx can be found at https://software.intel.com/en-us/articles/refer-ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.OperationVEXP2PD (KL, VL) = (8, 512)FOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask* THENIF (EVEX.b = 1) AND (SRC *is memory*)THEN DEST[i+63:i] := EXP2_23_DP(SRC[63:0])ELSE DEST[i+63:i] := EXP2_23_DP(SRC[i+63:i])FI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+63:i] := 0FI;FI;ENDFOR;Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.512.66.0F38.W1 C8 /rVEXP2PD zmm1 {k1}{z}, zmm2/m512/m64bcst {sae}AV/VAVX512ERComputes approximations to the exponential 2^x (with less than 2^-23 of maximum relative error) of the packed double-precision floating-point values from zmm2/m512/m64bcst and stores the floating-point result in zmm1with writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4AFullModRM:reg (r, w)ModRM:r/m (r)NANA

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentVEXP2PD __m512d _mm512_exp2a23_round_pd (__m512d a, int sae);VEXP2PD __m512d _mm512_mask_exp2a23_round_pd (__m512d a, __mmask8 m, __m512d b, int sae);VEXP2PD __m512d _mm512_maskz_exp2a23_round_pd ( __mmask8 m, __m512d b, int sae);SIMD Floating-Point ExceptionsInvalid (if SNaN input), OverflowOther ExceptionsSee Table2-46, “Type E2 Class Exception Conditions”.Table 6-1. Special Values BehaviorSource InputResultCommentsNaNQNaN(src)If (SRC = SNaN) then #I+++/-01.0fExact result-+0.0fIntegral value N2^ (N)Exact result

This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.