image/svg+xmlVCVTUSI2SS—Convert Unsigned Integer to Scalar Single-Precision Floating-Point ValueInstruction Operand EncodingDescriptionConverts a unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the source operand (second operand) to a single-precision floating-point value in the destination operand (first operand). The source operand can be a general-purpose register or a memory location. The destination operand is an XMM register. The result is stored in the low doubleword of the destination operand. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits.The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and destination operands are XMM registers. Bits (127:32) of the XMM register destination are copied from corre-sponding bits in the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.EVEX.W1 version: promotes the instruction to use 64-bit input value in 64-bit mode.OperationVCVTUSI2SS (EVEX encoded version)IF (SRC2 *is register*) AND (EVEX.b = 1) THENSET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);FI;IF 64-Bit Mode And OperandSize = 64THENDEST[31:0] := Convert_UInteger_To_Single_Precision_Floating_Point(SRC[63:0]);ELSEDEST[31:0] := Convert_UInteger_To_Single_Precision_Floating_Point(SRC[31:0]);FI;DEST[127:32] := SRC1[127:32]DEST[MAXVL-1:128] := 0Intel C/C++ Compiler Intrinsic EquivalentVCVTUSI2SS __m128 _mm_cvtu32_ss( __m128 s, unsigned a);VCVTUSI2SS __m128 _mm_cvt_roundu32_ss( __m128 s, unsigned a, int r);VCVTUSI2SS __m128 _mm_cvtu64_ss( __m128 s, unsigned __int64 a);VCVTUSI2SS __m128 _mm_cvt_roundu64_ss( __m128 s, unsigned __int64 a, int r);Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.LLIG.F3.0F.W0 7B /rVCVTUSI2SS xmm1, xmm2, r/m32{er}AV/VAVX512FConvert one signed doubleword integer from r/m32 to one single-precision floating-point value in xmm1.EVEX.LLIG.F3.0F.W1 7B /rVCVTUSI2SS xmm1, xmm2, r/m64{er}AV/N.E.1NOTES:1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version isused.AVX512FConvert one signed quadword integer from r/m64 to one single-precision floating-point value in xmm1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ATuple1 ScalarModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlSIMD Floating-Point ExceptionsPrecisionOther ExceptionsSee Table2-48, “Type E3NF Class Exception Conditions”.

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