image/svg+xmlVCVTUQQ2PS—Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point ValuesInstruction Operand EncodingDescriptionConverts packed unsigned quadword integers in the source operand (second operand) to single-precision floating-point values in the destination operand (first operand). EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a YMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1. Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.OperationVCVTUQQ2PS (EVEX encoded version) when src operand is a register(KL, VL) = (2, 128), (4, 256), (8, 512)IF (VL = 512) AND (EVEX.b = 1) THENSET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);FI;FOR j := 0 TO KL-1i := j * 32k := j * 64IF k1[j] OR *no writemask*THEN DEST[i+31:i] :=Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[k+63:k])ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL/2] := 0Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.128.F2.0F.W1 7A /rVCVTUQQ2PS xmm1 {k1}{z}, xmm2/m128/m64bcst AV/VAVX512VLAVX512DQConvert two packed unsigned quadword integers from xmm2/m128/m64bcst to packed single-precision floating-point values in zmm1 with writemask k1.EVEX.256.F2.0F.W1 7A /rVCVTUQQ2PS xmm1 {k1}{z}, ymm2/m256/m64bcstAV/VAVX512VLAVX512DQConvert four packed unsigned quadword integers from ymm2/m256/m64bcst to packed single-precision floating-point values in xmm1 with writemask k1.EVEX.512.F2.0F.W1 7A /rVCVTUQQ2PS ymm1 {k1}{z}, zmm2/m512/m64bcst{er}AV/VAVX512DQConvert eight packed unsigned quadword integers from zmm2/m512/m64bcst to eight packed single-precision floating-point values in zmm1 with writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4AFullModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlVCVTUQQ2PS (EVEX encoded version) when src operand is a memory source(KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 32k := j * 64IF k1[j] OR *no writemask*THEN IF (EVEX.b = 1) THENDEST[i+31:i] :=Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[63:0])ELSE DEST[i+31:i] :=Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[k+63:k])FI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL/2] := 0Intel C/C++ Compiler Intrinsic EquivalentVCVTUQQ2PS __m256 _mm512_cvtepu64_ps( __m512i a);VCVTUQQ2PS __m256 _mm512_mask_cvtepu64_ps( __m256 s, __mmask8 k, __m512i a);VCVTUQQ2PS __m256 _mm512_maskz_cvtepu64_ps( __mmask8 k, __m512i a);VCVTUQQ2PS __m256 _mm512_cvt_roundepu64_ps( __m512i a, int r);VCVTUQQ2PS __m256 _mm512_mask_cvt_roundepu64_ps( __m256 s, __mmask8 k, __m512i a, int r);VCVTUQQ2PS __m256 _mm512_maskz_cvt_roundepu64_ps( __mmask8 k, __m512i a, int r);VCVTUQQ2PS __m128 _mm256_cvtepu64_ps( __m256i a);VCVTUQQ2PS __m128 _mm256_mask_cvtepu64_ps( __m128 s, __mmask8 k, __m256i a);VCVTUQQ2PS __m128 _mm256_maskz_cvtepu64_ps( __mmask8 k, __m256i a);VCVTUQQ2PS __m128 _mm_cvtepu64_ps( __m128i a);VCVTUQQ2PS __m128 _mm_mask_cvtepu64_ps( __m128 s, __mmask8 k, __m128i a);VCVTUQQ2PS __m128 _mm_maskz_cvtepu64_ps( __mmask8 k, __m128i a);SIMD Floating-Point ExceptionsPrecisionOther ExceptionsEVEX-encoded instructions, see Table2-46, “Type E2 Class Exception Conditions”; additionally:#UDIf EVEX.vvvv != 1111B.

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