image/svg+xmlVCVTTSS2USI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned IntegerInstruction Operand EncodingDescriptionConverts with truncation a single-precision floating-point value in the source operand (the second operand) to an unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand (the first operand). The source operand can be an XMM register or a memory location. The destination operand is a general-purpose register. When the source operand is an XMM register, the single-precision floating-point value is contained in the low doubleword of the register.When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.EVEX.W1 version: promotes the instruction to produce 64-bit data in 64-bit mode.Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.OperationVCVTTSS2USI (EVEX encoded version)IF 64-bit Mode and OperandSize = 64THENDEST[63:0] := Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0]);ELSEDEST[31:0] := Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0]);FI;Intel C/C++ Compiler Intrinsic EquivalentVCVTTSS2USI unsigned int _mm_cvttss_u32( __m128 a);VCVTTSS2USI unsigned int _mm_cvtt_roundss_u32( __m128 a, int sae);VCVTTSS2USI unsigned __int64 _mm_cvttss_u64( __m128 a);VCVTTSS2USI unsigned __int64 _mm_cvtt_roundss_u64( __m128 a, int sae);SIMD Floating-Point ExceptionsInvalid, PrecisionOther ExceptionsEVEX-encoded instructions, see Table2-48, “Type E3NF Class Exception Conditions”.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.LLIG.F3.0F.W0 78 /rVCVTTSS2USI r32, xmm1/m32{sae}AV/VAVX512FConvert one single-precision floating-point value from xmm1/m32 to one unsigned doubleword integer in r32 using truncation.EVEX.LLIG.F3.0F.W1 78 /rVCVTTSS2USI r64, xmm1/m32{sae}AV/N.E.1NOTES:1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version isused.AVX512FConvert one single-precision floating-point value from xmm1/m32 to one unsigned quadword integer in r64 using truncation.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ATuple1 FixedModRM:reg (w)ModRM:r/m (r)NANA

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