image/svg+xmlVCVTTPS2QQ—Convert with Truncation Packed Single Precision Floating-Point Values to Packed Signed Quadword Integer ValuesInstruction Operand EncodingDescriptionConverts with truncation packed single-precision floating-point values in the source operand to eight signed quad-word integers in the destination operand.When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (2w-1, where w represents the number of bits in the destination format) is returned.EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64 bits) register or a 256/128/64-bit memory location. The destination operation is a vector register conditionally updated with writemask k1. Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.OperationVCVTTPS2QQ (EVEX encoded versions) when src operand is a register(KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64k := j * 32IF k1[j] OR *no writemask*THEN DEST[i+63:i] :=Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k])ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+63:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.128.66.0F.W0 7A /rVCVTTPS2QQ xmm1 {k1}{z}, xmm2/m64/m32bcstAV/VAVX512VLAVX512DQConvert two packed single precision floating-point values from xmm2/m64/m32bcst to two packed signed quadword values in xmm1 using truncation subject to writemask k1.EVEX.256.66.0F.W0 7A /rVCVTTPS2QQ ymm1 {k1}{z}, xmm2/m128/m32bcstAV/VAVX512VLAVX512DQConvert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed signed quadword values in ymm1 using truncation subject to writemask k1.EVEX.512.66.0F.W0 7A /rVCVTTPS2QQ zmm1 {k1}{z}, ymm2/m256/m32bcst{sae}AV/VAVX512DQConvert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed signed quadword values in zmm1 using truncation subject to writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4AHalfModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlVCVTTPS2QQ (EVEX encoded versions) when src operand is a memory source(KL, VL) = (2, 128), (4, 256), (8, 512)FOR j := 0 TO KL-1i := j * 64k := j * 32IF k1[j] OR *no writemask*THEN IF (EVEX.b == 1) THENDEST[i+63:i] :=Convert_Single_Precision_To_QuadInteger_Truncate(SRC[31:0])ELSE DEST[i+63:i] :=Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k])FI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+63:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0Intel C/C++ Compiler Intrinsic EquivalentVCVTTPS2QQ __m512i _mm512_cvttps_epi64( __m256 a);VCVTTPS2QQ __m512i _mm512_mask_cvttps_epi64( __m512i s, __mmask16 k, __m256 a);VCVTTPS2QQ __m512i _mm512_maskz_cvttps_epi64( __mmask16 k, __m256 a);VCVTTPS2QQ __m512i _mm512_cvtt_roundps_epi64( __m256 a, int sae);VCVTTPS2QQ __m512i _mm512_mask_cvtt_roundps_epi64( __m512i s, __mmask16 k, __m256 a, int sae);VCVTTPS2QQ __m512i _mm512_maskz_cvtt_roundps_epi64( __mmask16 k, __m256 a, int sae);VCVTTPS2QQ __m256i _mm256_mask_cvttps_epi64( __m256i s, __mmask8 k, __m128 a);VCVTTPS2QQ __m256i _mm256_maskz_cvttps_epi64( __mmask8 k, __m128 a);VCVTTPS2QQ __m128i _mm_mask_cvttps_epi64( __m128i s, __mmask8 k, __m128 a);VCVTTPS2QQ __m128i _mm_maskz_cvttps_epi64( __mmask8 k, __m128 a);SIMD Floating-Point ExceptionsInvalid, PrecisionOther ExceptionsEVEX-encoded instructions, see Table2-47, “Type E3 Class Exception Conditions”; additionally:#UDIf EVEX.vvvv != 1111B.

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