image/svg+xmlVCVTPS2UDQ—Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer ValuesInstruction Operand EncodingDescriptionConverts sixteen packed single-precision floating-point values in the source operand to sixteen unsigned double-word integers in the destination operand.When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1. Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.128.0F.W0 79 /rVCVTPS2UDQ xmm1 {k1}{z}, xmm2/m128/m32bcstAV/VAVX512VLAVX512FConvert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed unsigned doubleword values in xmm1 subject to writemask k1.EVEX.256.0F.W0 79 /rVCVTPS2UDQ ymm1 {k1}{z}, ymm2/m256/m32bcstAV/VAVX512VLAVX512FConvert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed unsigned doubleword values in ymm1 subject to writemask k1.EVEX.512.0F.W0 79 /rVCVTPS2UDQ zmm1 {k1}{z}, zmm2/m512/m32bcst{er}AV/VAVX512FConvert sixteen packed single-precision floating-point values from zmm2/m512/m32bcst to sixteen packed unsigned doubleword values in zmm1 subject to writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4AFullModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlOperationVCVTPS2UDQ (EVEX encoded versions) when src operand is a register(KL, VL) = (4, 128), (8, 256), (16, 512)IF (VL = 512) AND (EVEX.b = 1) THENSET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);FI;FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask*THEN DEST[i+31:i] :=Convert_Single_Precision_Floating_Point_To_UInteger(SRC[i+31:i])ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0VCVTPS2UDQ (EVEX encoded versions) when src operand is a memory source(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no *THEN IF (EVEX.b = 1) THENDEST[i+31:i] :=Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0])ELSE DEST[i+31:i] :=Convert_Single_Precision_Floating_Point_To_UInteger(SRC[i+31:i])FI;ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentVCVTPS2UDQ __m512i _mm512_cvtps_epu32( __m512 a);VCVTPS2UDQ __m512i _mm512_mask_cvtps_epu32( __m512i s, __mmask16 k, __m512 a);VCVTPS2UDQ __m512i _mm512_maskz_cvtps_epu32( __mmask16 k, __m512 a);VCVTPS2UDQ __m512i _mm512_cvt_roundps_epu32( __m512 a, int r);VCVTPS2UDQ __m512i _mm512_mask_cvt_roundps_epu32( __m512i s, __mmask16 k, __m512 a, int r);VCVTPS2UDQ __m512i _mm512_maskz_cvt_roundps_epu32( __mmask16 k, __m512 a, int r);VCVTPS2UDQ __m256i _mm256_cvtps_epu32( __m256d a);VCVTPS2UDQ __m256i _mm256_mask_cvtps_epu32( __m256i s, __mmask8 k, __m256 a);VCVTPS2UDQ __m256i _mm256_maskz_cvtps_epu32( __mmask8 k, __m256 a);VCVTPS2UDQ __m128i _mm_cvtps_epu32( __m128 a);VCVTPS2UDQ __m128i _mm_mask_cvtps_epu32( __m128i s, __mmask8 k, __m128 a);VCVTPS2UDQ __m128i _mm_maskz_cvtps_epu32( __mmask8 k, __m128 a);SIMD Floating-Point ExceptionsInvalid, PrecisionOther ExceptionsEVEX-encoded instructions, see Table2-46, “Type E2 Class Exception Conditions”; additionally:#UDIf EVEX.vvvv != 1111B.

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