image/svg+xml VCVTPS2QQ—Convert Packed Single Precision Floating-Point Values to Packed Signed Quadword Integer Values Instruction Operand Encoding Description Converts eight packed single-precision floating-point values in the source operand to eight signed quadword inte- gers in the destination operand. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (2 w -1, where w represents the number of bits in the destination format) is returned. The source operand is a YMM/XMM/XMM (low 64- bits) register or a 256/128/64-bit memory location. The destina- tion operation is a ZMM/YMM/XMM register conditionally updated with writemask k1. Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. Opcode/ Instruction Op / En 64/32 bit Mode Support CPUID Feature Flag Description EVEX.128.66.0F.W0 7B /r VCVTPS2QQ xmm1 {k1}{z}, xmm2/m64/m32bcst AV/VAVX512VL AVX512DQ Convert two packed single precision floating-point values from xmm2/m64/m32bcst to two packed signed quadword values in xmm1 subject to writemask k1. EVEX.256.66.0F.W0 7B /r VCVTPS2QQ ymm1 {k1}{z}, xmm2/m128/m32bcst AV/VAVX512VL AVX512DQ Convert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed signed quadword values in ymm1 subject to writemask k1. EVEX.512.66.0F.W0 7B /r VCVTPS2QQ zmm1 {k1}{z}, ymm2/m256/m32bcst{er} AV/VAVX512DQConvert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed signed quadword values in zmm1 subject to writemask k1. Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4 AHalfModRM:reg (w)ModRM:r/m (r)NANA image/svg+xml Operation VCVTPS2QQ (EVEX encoded versions) when src operand is a register (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL == 512) AND (EVEX.b == 1) THEN SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC); ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC); FI; FOR j := 0 TO KL-1 i := j * 64 k := j * 32 IF k1[j] OR *no writemask* THEN DEST[i+63:i] := Convert_Single_Precision_To_QuadInteger(SRC[k+31:k]) ELSE IF *merging-masking*; merging-masking THEN *DEST[i+63:i] remains unchanged* ELSE ; zeroing-masking DEST[i+63:i] := 0 FI FI; ENDFOR DEST[MAXVL-1:VL] := 0 VCVTPS2QQ (EVEX encoded versions) when src operand is a memory source (KL, VL) = (2, 128), (4, 256), (8, 512) FOR j := 0 TO KL-1 i := j * 64 k := j * 32 IF k1[j] OR *no writemask* THEN IF (EVEX.b == 1) THEN DEST[i+63:i] := Convert_Single_Precision_To_QuadInteger(SRC[31:0]) ELSE DEST[i+63:i] := Convert_Single_Precision_To_QuadInteger(SRC[k+31:k]) FI; ELSE IF *merging-masking*; merging-masking THEN *DEST[i+63:i] remains unchanged* ELSE ; zeroing-masking DEST[i+63:i] := 0 FI FI; ENDFOR DEST[MAXVL-1:VL] := 0 image/svg+xml Intel C/C++ Compiler Intrinsic Equivalent VCVTPS2QQ __m512i _mm512_cvtps_epi64( __m512 a); VCVTPS2QQ __m512i _mm512_mask_cvtps_epi64( __m512i s, __mmask16 k, __m512 a); VCVTPS2QQ __m512i _mm512_maskz_cvtps_epi64( __mmask16 k, __m512 a); VCVTPS2QQ __m512i _mm512_cvt_roundps_epi64( __m512 a, int r); VCVTPS2QQ __m512i _mm512_mask_cvt_roundps_epi64( __m512i s, __mmask16 k, __m512 a, int r); VCVTPS2QQ __m512i _mm512_maskz_cvt_roundps_epi64( __mmask16 k, __m512 a, int r); VCVTPS2QQ __m256i _mm256_cvtps_epi64( __m256 a); VCVTPS2QQ __m256i _mm256_mask_cvtps_epi64( __m256i s, __mmask8 k, __m256 a); VCVTPS2QQ __m256i _mm256_maskz_cvtps_epi64( __mmask8 k, __m256 a); VCVTPS2QQ __m128i _mm_cvtps_epi64( __m128 a); VCVTPS2QQ __m128i _mm_mask_cvtps_epi64( __m128i s, __mmask8 k, __m128 a); VCVTPS2QQ __m128i _mm_maskz_cvtps_epi64( __mmask8 k, __m128 a); SIMD Floating-Point Exceptions Invalid, Precision Other Exceptions EVEX-encoded instructions, see Table2-47, “Type E3 Class Exception Conditions”; additionally: #UDIf EVEX.vvvv != 1111B. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .