VCVTPS2PH—Convert Single-Precision FP value to 16-bit FP valueInstruction Operand EncodingDescriptionConvert packed single-precision floating values in the source operand to half-precision (16-bit) floating-point values and store to the destination operand. The rounding mode is specified using the immediate field (imm8).Underflow results (i.e., tiny results) are converted to denormals. MXCSR.FTZ is ignored. If a source element is denormal relative to the input format with DM masked and at least one of PM or UM unmasked; a SIMD exception will be raised with DE, UE and PE set.The immediate byte defines several bit fields that control rounding operation. The effect and encoding of the RC field are listed in Table 5-3.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionVEX.128.66.0F3A.W0 1D /r ibVCVTPS2PH xmm1/m64, xmm2, imm8AV/VF16CConvert four packed single-precision floating-point values in xmm2 to packed half-precision (16-bit) floating-point values in xmm1/m64. Imm8 provides rounding controls.VEX.256.66.0F3A.W0 1D /r ibVCVTPS2PH xmm1/m128, ymm2, imm8AV/VF16CConvert eight packed single-precision floating-point values in ymm2 to packed half-precision (16-bit) floating-point values in xmm1/m128. Imm8 provides rounding controls.EVEX.128.66.0F3A.W0 1D /r ibVCVTPS2PH xmm1/m64 {k1}{z}, xmm2, imm8BV/VAVX512VLAVX512FConvert four packed single-precision floating-point values in xmm2 to packed half-precision (16-bit) floating-point values in xmm1/m64. Imm8 provides rounding controls.EVEX.256.66.0F3A.W0 1D /r ibVCVTPS2PH xmm1/m128 {k1}{z}, ymm2, imm8BV/VAVX512VLAVX512FConvert eight packed single-precision floating-point values in ymm2 to packed half-precision (16-bit) floating-point values in xmm1/m128. Imm8 provides rounding controls.EVEX.512.66.0F3A.W0 1D /r ibVCVTPS2PH ymm1/m256 {k1}{z}, zmm2{sae}, imm8BV/VAVX512FConvert sixteen packed single-precision floating-point values in zmm2 to packed half-precision (16-bit) floating-point values in ymm1/m256. Imm8 provides rounding controls.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:r/m (w)ModRM:reg (r)Imm8NABHalf MemModRM:r/m (w)ModRM:reg (r)Imm8NAFigure 5-7. VCVTPS2PH (128-bit Version)VH0VH1VH2VH315 031 1647 3263 4895 64127 96VS0VS1VS2VS331 063 3295 64127 96xmm1/mem64xmm2VCVTPS2PH xmm1/mem64, xmm2, imm8convertconvertconvertconvert
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