image/svg+xmlVCVTPS2PH—Convert Single-Precision FP value to 16-bit FP valueInstruction Operand EncodingDescriptionConvert packed single-precision floating values in the source operand to half-precision (16-bit) floating-point values and store to the destination operand. The rounding mode is specified using the immediate field (imm8).Underflow results (i.e., tiny results) are converted to denormals. MXCSR.FTZ is ignored. If a source element is denormal relative to the input format with DM masked and at least one of PM or UM unmasked; a SIMD exception will be raised with DE, UE and PE set.The immediate byte defines several bit fields that control rounding operation. The effect and encoding of the RC field are listed in Table 5-3.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionVEX.128.66.0F3A.W0 1D /r ibVCVTPS2PH xmm1/m64, xmm2, imm8AV/VF16CConvert four packed single-precision floating-point values in xmm2 to packed half-precision (16-bit) floating-point values in xmm1/m64. Imm8 provides rounding controls.VEX.256.66.0F3A.W0 1D /r ibVCVTPS2PH xmm1/m128, ymm2, imm8AV/VF16CConvert eight packed single-precision floating-point values in ymm2 to packed half-precision (16-bit) floating-point values in xmm1/m128. Imm8 provides rounding controls.EVEX.128.66.0F3A.W0 1D /r ibVCVTPS2PH xmm1/m64 {k1}{z}, xmm2, imm8BV/VAVX512VLAVX512FConvert four packed single-precision floating-point values in xmm2 to packed half-precision (16-bit) floating-point values in xmm1/m64. Imm8 provides rounding controls.EVEX.256.66.0F3A.W0 1D /r ibVCVTPS2PH xmm1/m128 {k1}{z}, ymm2, imm8BV/VAVX512VLAVX512FConvert eight packed single-precision floating-point values in ymm2 to packed half-precision (16-bit) floating-point values in xmm1/m128. Imm8 provides rounding controls.EVEX.512.66.0F3A.W0 1D /r ibVCVTPS2PH ymm1/m256 {k1}{z}, zmm2{sae}, imm8BV/VAVX512FConvert sixteen packed single-precision floating-point values in zmm2 to packed half-precision (16-bit) floating-point values in ymm1/m256. Imm8 provides rounding controls.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:r/m (w)ModRM:reg (r)Imm8NABHalf MemModRM:r/m (w)ModRM:reg (r)Imm8NAFigure 5-7. VCVTPS2PH (128-bit Version)VH0VH1VH2VH315 031 1647 3263 4895 64127 96VS0VS1VS2VS331 063 3295 64127 96xmm1/mem64xmm2VCVTPS2PH xmm1/mem64, xmm2, imm8convertconvertconvertconvert

image/svg+xmlVEX.128 version: The source operand is a XMM register. The destination operand is a XMM register or 64-bit memory location. If the destination operand is a register then the upper bits (MAXVL-1:64) of corresponding register are zeroed.VEX.256 version: The source operand is a YMM register. The destination operand is a XMM register or 128-bit memory location. If the destination operand is a register, the upper bits (MAXVL-1:128) of the corresponding desti-nation register are zeroed.Note: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).EVEX encoded versions: The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM (low 64-bits) register or a 256/128/64-bit memory location, conditionally updated with writemask k1. Bits (MAXVL-1:256/128/64) of the corresponding destination register are zeroed.OperationvCvt_s2h(SRC1[31:0]){IF Imm[2] = 0THEN ; using Imm[1:0] for rounding control, see Table 5-3RETURN Cvt_Single_Precision_To_Half_Precision_FP_Imm(SRC1[31:0]);ELSE ; using MXCSR.RC for rounding controlRETURN Cvt_Single_Precision_To_Half_Precision_FP_Mxcsr(SRC1[31:0]);FI;}VCVTPS2PH (EVEX encoded versions) when dest is a register(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 16k := j * 32IF k1[j] OR *no writemask*THEN DEST[i+15:i] :=vCvt_s2h(SRC[k+31:k])ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+15:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+15:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL/2] := 0Table 5-3. Immediate Byte Encoding for 16-bit Floating-Point Conversion InstructionsBitsField Name/valueDescriptionCommentImm[1:0]RC=00BRound to nearest evenIf Imm[2] = 0RC=01BRound downRC=10BRound upRC=11BTruncateImm[2]MS1=0Use imm[1:0] for roundingIgnore MXCSR.RC MS1=1Use MXCSR.RC for roundingImm[7:3]IgnoredIgnored by processor

image/svg+xmlVCVTPS2PH (EVEX encoded versions) when dest is memory(KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 16k := j * 32IF k1[j] OR *no writemask*THEN DEST[i+15:i] :=vCvt_s2h(SRC[k+31:k])ELSE *DEST[i+15:i] remains unchanged*; merging-maskingFI;ENDFORVCVTPS2PH (VEX.256 encoded version)DEST[15:0] := vCvt_s2h(SRC1[31:0]);DEST[31:16] := vCvt_s2h(SRC1[63:32]);DEST[47:32] := vCvt_s2h(SRC1[95:64]);DEST[63:48] := vCvt_s2h(SRC1[127:96]);DEST[79:64] := vCvt_s2h(SRC1[159:128]);DEST[95:80] := vCvt_s2h(SRC1[191:160]);DEST[111:96] := vCvt_s2h(SRC1[223:192]);DEST[127:112] := vCvt_s2h(SRC1[255:224]);DEST[MAXVL-1:128] := 0VCVTPS2PH (VEX.128 encoded version) DEST[15:0] := vCvt_s2h(SRC1[31:0]);DEST[31:16] := vCvt_s2h(SRC1[63:32]);DEST[47:32] := vCvt_s2h(SRC1[95:64]);DEST[63:48] := vCvt_s2h(SRC1[127:96]);DEST[MAXVL-1:64] := 0Flags AffectedNoneIntel C/C++ Compiler Intrinsic EquivalentVCVTPS2PH __m256i _mm512_cvtps_ph(__m512 a);VCVTPS2PH __m256i _mm512_mask_cvtps_ph(__m256i s, __mmask16 k,__m512 a);VCVTPS2PH __m256i _mm512_maskz_cvtps_ph(__mmask16 k,__m512 a);VCVTPS2PH __m256i _mm512_cvt_roundps_ph(__m512 a, const int imm);VCVTPS2PH __m256i _mm512_mask_cvt_roundps_ph(__m256i s, __mmask16 k,__m512 a, const int imm);VCVTPS2PH __m256i _mm512_maskz_cvt_roundps_ph(__mmask16 k,__m512 a, const int imm);VCVTPS2PH __m128i _mm256_mask_cvtps_ph(__m128i s, __mmask8 k,__m256 a);VCVTPS2PH __m128i _mm256_maskz_cvtps_ph(__mmask8 k,__m256 a);VCVTPS2PH __m128i _mm_mask_cvtps_ph(__m128i s, __mmask8 k,__m128 a);VCVTPS2PH __m128i _mm_maskz_cvtps_ph(__mmask8 k,__m128 a);VCVTPS2PH __m128i _mm_cvtps_ph ( __m128 m1, const int imm);VCVTPS2PH __m128i _mm256_cvtps_ph(__m256 m1, const int imm);SIMD Floating-Point ExceptionsInvalid, Underflow, Overflow, Precision, Denormal (if MXCSR.DAZ=0);

image/svg+xmlOther ExceptionsVEX-encoded instructions, see Table2-26, “Type 11 Class Exception Conditions” (do not report #AC); EVEX-encoded instructions, see Table2-60, “Type E11 Class Exception Conditions”.Additionally:#UDIf VEX.W=1.#UDIf VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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