image/svg+xmlVCVTPH2PS—Convert 16-bit FP values to Single-Precision FP valuesInstruction Operand EncodingDescriptionConverts packed half precision (16-bits) floating-point values in the low-order bits of the source operand (the second operand) to packed single-precision floating-point values and writes the converted values into the destina-tion operand (the first operand).If case of a denormal operand, the correct normal result is returned. MXCSR.DAZ is ignored and is treated as if it 0. No denormal exception is reported on MXCSR.VEX.128 version: The source operand is a XMM register or 64-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding destination register are zeroed.VEX.256 version: The source operand is a XMM register or 128-bit memory location. The destination operand is a YMM register. Bits (MAXVL-1:256) of the corresponding destination register are zeroed.EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64-bits) register or a 256/128/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1. The diagram below illustrates how data is converted from four packed half precision (in 64 bits) to four single preci-sion (in 128 bits) FP values.Note: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionVEX.128.66.0F38.W0 13 /r VCVTPH2PS xmm1, xmm2/m64AV/VF16CConvert four packed half precision (16-bit) floating-point values in xmm2/m64 to packed single-precision floating-point value in xmm1. VEX.256.66.0F38.W0 13 /r VCVTPH2PS ymm1, xmm2/m128AV/VF16CConvert eight packed half precision (16-bit) floating-point values in xmm2/m128 to packed single-precision floating-point value in ymm1. EVEX.128.66.0F38.W0 13 /r VCVTPH2PS xmm1 {k1}{z}, xmm2/m64BV/VAVX512VLAVX512FConvert four packed half precision (16-bit) floating-point values in xmm2/m64 to packed single-precision floating-point values in xmm1. EVEX.256.66.0F38.W0 13 /r VCVTPH2PS ymm1 {k1}{z}, xmm2/m128BV/VAVX512VLAVX512FConvert eight packed half precision (16-bit) floating-point values in xmm2/m128 to packed single-precision floating-point values in ymm1. EVEX.512.66.0F38.W0 13 /r VCVTPH2PS zmm1 {k1}{z}, ymm2/m256 {sae}BV/VAVX512FConvert sixteen packed half precision (16-bit) floating-point values in ymm2/m256 to packed single-precision floating-point values in zmm1. Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (w)ModRM:r/m (r)NANABHalf MemModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlOperationvCvt_h2s(SRC1[15:0]){RETURN Cvt_Half_Precision_To_Single_Precision(SRC1[15:0]);}VCVTPH2PS (EVEX encoded versions) (KL, VL) = (4, 128), (8, 256), (16, 512)FOR j := 0 TO KL-1i := j * 32k := j * 16IF k1[j] OR *no writemask*THEN DEST[i+31:i] :=vCvt_h2s(SRC[k+15:k])ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFORDEST[MAXVL-1:VL] := 0VCVTPH2PS (VEX.256 encoded version)DEST[31:0] := vCvt_h2s(SRC1[15:0]);DEST[63:32] := vCvt_h2s(SRC1[31:16]);DEST[95:64] := vCvt_h2s(SRC1[47:32]);DEST[127:96] := vCvt_h2s(SRC1[63:48]);DEST[159:128] := vCvt_h2s(SRC1[79:64]);DEST[191:160] := vCvt_h2s(SRC1[95:80]);DEST[223:192] := vCvt_h2s(SRC1[111:96]);DEST[255:224] := vCvt_h2s(SRC1[127:112]);DEST[MAXVL-1:256] := 0Figure 5-6. VCVTPH2PS (128-bit Version)VH0VH1VH2VH315 031 1647 3263 4895 64127 96VS0VS1VS2VS331 063 3295 64127 96convertconvertconvertconvertxmm2/mem64xmm1VCVTPH2PS xmm1, xmm2/mem64, imm8

image/svg+xmlVCVTPH2PS (VEX.128 encoded version) DEST[31:0] := vCvt_h2s(SRC1[15:0]);DEST[63:32] := vCvt_h2s(SRC1[31:16]);DEST[95:64] := vCvt_h2s(SRC1[47:32]);DEST[127:96] := vCvt_h2s(SRC1[63:48]);DEST[MAXVL-1:128] := 0Flags AffectedNoneIntel C/C++ Compiler Intrinsic EquivalentVCVTPH2PS __m512 _mm512_cvtph_ps( __m256i a);VCVTPH2PS __m512 _mm512_mask_cvtph_ps(__m512 s, __mmask16 k, __m256i a);VCVTPH2PS __m512 _mm512_maskz_cvtph_ps(__mmask16 k, __m256i a);VCVTPH2PS __m512 _mm512_cvt_roundph_ps( __m256i a, int sae);VCVTPH2PS __m512 _mm512_mask_cvt_roundph_ps(__m512 s, __mmask16 k, __m256i a, int sae);VCVTPH2PS __m512 _mm512_maskz_cvt_roundph_ps( __mmask16 k, __m256i a, int sae);VCVTPH2PS __m256 _mm256_mask_cvtph_ps(__m256 s, __mmask8 k, __m128i a);VCVTPH2PS __m256 _mm256_maskz_cvtph_ps(__mmask8 k, __m128i a);VCVTPH2PS __m128 _mm_mask_cvtph_ps(__m128 s, __mmask8 k, __m128i a);VCVTPH2PS __m128 _mm_maskz_cvtph_ps(__mmask8 k, __m128i a);VCVTPH2PS __m128 _mm_cvtph_ps ( __m128i m1);VCVTPH2PS __m256 _mm256_cvtph_ps ( __m128i m1)SIMD Floating-Point ExceptionsInvalidOther ExceptionsVEX-encoded instructions, see Table2-26, “Type 11 Class Exception Conditions” (do not report #AC).EVEX-encoded instructions, see Table2-60, “Type E11 Class Exception Conditions”.Additionally:#UDIf VEX.W=1.#UDIf VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

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