VCVTPD2UQQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword IntegersInstruction Operand EncodingDescriptionConverts packed double-precision floating-point values in the source operand (second operand) to packed unsigned quadword integers in the destination operand (first operand). When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w – 1 is returned, where w represents the number of bits in the destination format.The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1. EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.128.66.0F.W1 79 /rVCVTPD2UQQ xmm1 {k1}{z}, xmm2/m128/m64bcst AV/VAVX512VLAVX512DQConvert two packed double-precision floating-point values from xmm2/mem to two packed unsigned quadword integers in xmm1 with writemask k1.EVEX.256.66.0F.W1 79 /rVCVTPD2UQQ ymm1 {k1}{z}, ymm2/m256/m64bcstAV/VAVX512VLAVX512DQConvert fourth packed double-precision floating-point values from ymm2/mem to four packed unsigned quadword integers in ymm1 with writemask k1.EVEX.512.66.0F.W1 79 /rVCVTPD2UQQ zmm1 {k1}{z}, zmm2/m512/m64bcst{er} AV/VAVX512DQConvert eight packed double-precision floating-point values from zmm2/mem to eight packed unsigned quadword integers in zmm1 with writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4AFullModRM:reg (w)ModRM:r/m (r)NANA
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