image/svg+xml VCVTPD2UDQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers Instruction Operand Encoding Description Converts packed double-precision floating-point values in the source operand (the second operand) to packed unsigned doubleword integers in the destination operand (the first operand). When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2 w – 1 is returned, where w represents the number of bits in the destination format. The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1. The upper bits (MAXVL-1:256) of the corresponding destination are zeroed. EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. Opcode Instruction Op / En 64/32 bit Mode Support CPUID Feature Flag Description EVEX.128.0F.W1 79 /r VCVTPD2UDQ xmm1 {k1}{z}, xmm2/m128/m64bcst AV/VAVX512VL AVX512F Convert two packed double-precision floating-point values in xmm2/m128/m64bcst to two unsigned doubleword integers in xmm1 subject to writemask k1. EVEX.256.0F.W1 79 /r VCVTPD2UDQ xmm1 {k1}{z}, ymm2/m256/m64bcst AV/VAVX512VL AVX512F Convert four packed double-precision floating-point values in ymm2/m256/m64bcst to four unsigned doubleword integers in xmm1 subject to writemask k1. EVEX.512.0F.W1 79 /r VCVTPD2UDQ ymm1 {k1}{z}, zmm2/m512/m64bcst{er} AV/VAVX512FConvert eight packed double-precision floating-point values in zmm2/m512/m64bcst to eight unsigned doubleword integers in ymm1 subject to writemask k1. Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4 AFullModRM:reg (w)ModRM:r/m (r)NANA image/svg+xml Operation VCVTPD2UDQ (EVEX encoded versions) when src2 operand is a register (KL, VL) = (2, 128), (4, 256), (8, 512) IF (VL = 512) AND (EVEX.b = 1) THEN SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC); ELSE SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC); FI; FOR j := 0 TO KL-1 i := j * 32 k := j * 64 IF k1[j] OR *no writemask* THEN DEST[i+31:i] := Convert_Double_Precision_Floating_Point_To_UInteger(SRC[k+63:k]) ELSE IF *merging-masking*; merging-masking THEN *DEST[i+31:i] remains unchanged* ELSE ; zeroing-masking DEST[i+31:i] := 0 FI FI; ENDFOR DEST[MAXVL-1:VL/2] := 0 VCVTPD2UDQ (EVEX encoded versions) when src operand is a memory source (KL, VL) = (2, 128), (4, 256), (8, 512) FOR j := 0 TO KL-1 i := j * 32 k := j * 64 IF k1[j] OR *no writemask* THEN IF (EVEX.b = 1) THEN DEST[i+31:i] := Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]) ELSE DEST[i+31:i] := Convert_Double_Precision_Floating_Point_To_UInteger(SRC[k+63:k]) FI; ELSE IF *merging-masking*; merging-masking THEN *DEST[i+31:i] remains unchanged* ELSE ; zeroing-masking DEST[i+31:i] := 0 FI FI; ENDFOR DEST[MAXVL-1:VL/2] := 0 image/svg+xml Intel C/C++ Compiler Intrinsic Equivalent VCVTPD2UDQ __m256i _mm512_cvtpd_epu32( __m512d a); VCVTPD2UDQ __m256i _mm512_mask_cvtpd_epu32( __m256i s, __mmask8 k, __m512d a); VCVTPD2UDQ __m256i _mm512_maskz_cvtpd_epu32( __mmask8 k, __m512d a); VCVTPD2UDQ __m256i _mm512_cvt_roundpd_epu32( __m512d a, int r); VCVTPD2UDQ __m256i _mm512_mask_cvt_roundpd_epu32( __m256i s, __mmask8 k, __m512d a, int r); VCVTPD2UDQ __m256i _mm512_maskz_cvt_roundpd_epu32( __mmask8 k, __m512d a, int r); VCVTPD2UDQ __m128i _mm256_mask_cvtpd_epu32( __m128i s, __mmask8 k, __m256d a); VCVTPD2UDQ __m128i _mm256_maskz_cvtpd_epu32( __mmask8 k, __m256d a); VCVTPD2UDQ __m128i _mm_mask_cvtpd_epu32( __m128i s, __mmask8 k, __m128d a); VCVTPD2UDQ __m128i _mm_maskz_cvtpd_epu32( __mmask8 k, __m128d a); SIMD Floating-Point Exceptions Invalid, Precision Other Exceptions EVEX-encoded instructions, see Table2-46, “Type E2 Class Exception Conditions”; additionally: #UDIf EVEX.vvvv != 1111B. This UNOFFICIAL reference was generated from the official Intel® 64 and IA-32 Architectures Software Developer’s Manual by a dumb script. There is no guarantee that some parts aren't mangled or broken and is distributed WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE .