image/svg+xmlVCVTNEPS2BF16—Convert Packed Single Data to Packed BF16 DataInstruction Operand EncodingDescriptionConverts one SIMD register of packed single data into a single register of packed BF16 data.This instruction uses “Round to nearest (even)” rounding mode. Output denormals are always flushed to zero and input denormals are always treated as zero. MXCSR is not consulted nor updated. As the instruction operand encoding table shows, the EVEX.vvvv field is not used for encoding an operand. EVEX.vvvv is reserved and must be 0b1111 otherwise instructions will #UD.OperationDefine convert_fp32_to_bfloat16(x):IF x is zero or denormal:dest[15] := x[31] // sign preserving zero (denormal go to zero)dest[14:0] := 0ELSE IF x is infinity:dest[15:0] := x[31:16]ELSE IF x is NAN:dest[15:0] := x[31:16] // truncate and set MSB of the mantissa to force QNANdest[6] := 1ELSE // normal numberLSB := x[16]rounding_bias := 0x00007FFF + LSBtemp[31:0] := x[31:0] + rounding_bias // integer adddest[15:0] := temp[31:16]RETURN destOpcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.128.F3.0F38.W0 72 /rVCVTNEPS2BF16 xmm1{k1}{z}, xmm2/m128/m32bcstAV/VAVX512VLAVX512_BF16Convert packed single data from xmm2/m128 to packed BF16 data in xmm1 with writemask k1.EVEX.256.F3.0F38.W0 72 /rVCVTNEPS2BF16 xmm1{k1}{z}, ymm2/m256/m32bcstAV/VAVX512VLAVX512_BF16Convert packed single data from ymm2/m256 to packed BF16 data in xmm1 with writemask k1.EVEX.512.F3.0F38.W0 72 /rVCVTNEPS2BF16 ymm1{k1}{z}, zmm2/m512/m32bcstAV/VAVX512FAVX512_BF16Convert packed single data from zmm2/m512 to packed BF16 data in ymm1 with writemask k1.Op/EnTupleOperand 1Operand 2Operand 3Operand 4AFullModRM:reg (w)ModRM:r/m (r)NANA

image/svg+xmlVCVTNEPS2BF16 dest, srcVL = (128, 256, 512)KL = VL/16origdest := destFOR i := 0 to KL/2-1:IF k1[ i ] or *no writemask*:IF src is memory and evex.b == 1:t := src.fp32[0]ELSE:t := src.fp32[ i ]dest.word[i] := convert_fp32_to_bfloat16(t)ELSE IF *zeroing*:dest.word[ i ] := 0ELSE: // Merge masking, dest element unchangeddest.word[ i ] := origdest.word[ i ]DEST[MAXVL-1:VL/2] := 0Intel C/C++ Compiler Intrinsic EquivalentVCVTNEPS2BF16 __m128bh _mm_cvtneps_pbh (__m128);VCVTNEPS2BF16 __m128bh _mm_mask_cvtneps_pbh (__m128bh, __mmask8, __m128);VCVTNEPS2BF16 __m128bh _mm_maskz_cvtneps_pbh (__mmask8, __m128);VCVTNEPS2BF16 __m128bh _mm256_cvtneps_pbh (__m256);VCVTNEPS2BF16 __m128bh _mm256_mask_cvtneps_pbh (__m128bh, __mmask8, __m256);VCVTNEPS2BF16 __m128bh _mm256_maskz_cvtneps_pbh (__mmask8, __m256);VCVTNEPS2BF16 __m256bh _mm512_cvtneps_pbh (__m512);VCVTNEPS2BF16 __m256bh _mm512_mask_cvtneps_pbh (__m256bh, __mmask16, __m512);VCVTNEPS2BF16 __m256bh _mm512_maskz_cvtneps_pbh (__mmask16, __m512);SIMD Floating-Point ExceptionsNone.Other ExceptionsSee Table2-49, “Type E4 Class Exception Conditions”.

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