image/svg+xmlVALIGND/VALIGNQ—Align Doubleword/Quadword VectorsInstruction Operand EncodingDescriptionConcatenates and shifts right doubleword/quadword elements of the first source operand (the second operand) and the second source operand (the third operand) into a 1024/512/256-bit intermediate vector. The low 512/256/128-bit of the intermediate vector is written to the destination operand (the first operand) using the writemask k1. The destination and first source operands are ZMM/YMM/XMM registers. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location.This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1 are computed and stored into zmm1. Elements in zmm1 with the corresponding bit clear in k1 retain their previous values (merging-masking) or are set to 0 (zeroing-masking).Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.128.66.0F3A.W0 03 /r ibVALIGND xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst, imm8AV/VAVX512VLAVX512FShift right and merge vectors xmm2 and xmm3/m128/m32bcst with double-word granularity using imm8 as number of elements to shift, and store the final result in xmm1, under writemask.EVEX.128.66.0F3A.W1 03 /r ibVALIGNQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst, imm8AV/VAVX512VLAVX512FShift right and merge vectors xmm2 and xmm3/m128/m64bcst with quad-word granularity using imm8 as number of elements to shift, and store the final result in xmm1, under writemask.EVEX.256.66.0F3A.W0 03 /r ibVALIGND ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst, imm8AV/VAVX512VLAVX512FShift right and merge vectors ymm2 and ymm3/m256/m32bcst with double-word granularity using imm8 as number of elements to shift, and store the final result in ymm1, under writemask.EVEX.256.66.0F3A.W1 03 /r ibVALIGNQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst, imm8AV/VAVX512VLAVX512FShift right and merge vectors ymm2 and ymm3/m256/m64bcst with quad-word granularity using imm8 as number of elements to shift, and store the final result in ymm1, under writemask.EVEX.512.66.0F3A.W0 03 /r ibVALIGND zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst, imm8AV/VAVX512FShift right and merge vectors zmm2 and zmm3/m512/m32bcst with double-word granularity using imm8 as number of elements to shift, and store the final result in zmm1, under writemask.EVEX.512.66.0F3A.W1 03 /r ibVALIGNQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst, imm8AV/VAVX512FShift right and merge vectors zmm2 and zmm3/m512/m64bcst with quad-word granularity using imm8 as number of elements to shift, and store the final result in zmm1, under writemask.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4AFullModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA

image/svg+xmlOperationVALIGND (EVEX encoded versions) (KL, VL) = (4, 128), (8, 256), (16, 512)IF (SRC2 *is memory*) (AND EVEX.b = 1)THEN FOR j := 0 TO KL-1i := j * 32src[i+31:i] := SRC2[31:0]ENDFOR;ELSE src := SRC2FI; Concatenate sourcestmp[VL-1:0] := src[VL-1:0]tmp[2VL-1:VL] := SRC1[VL-1:0]; Shift right doubleword elementsIF VL = 128THEN SHIFT = imm8[1:0]ELSE IF VL = 256THEN SHIFT = imm8[2:0]ELSE SHIFT = imm8[3:0]FIFI;tmp[2VL-1:0] := tmp[2VL-1:0] >> (32*SHIFT); Apply writemaskFOR j := 0 TO KL-1i := j * 32IF k1[j] OR *no writemask*THEN DEST[i+31:i] := tmp[i+31:i]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+31:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+31:i] := 0FIFI;ENDFOR;DEST[MAXVL-1:VL] := 0

image/svg+xmlVALIGNQ (EVEX encoded versions) (KL, VL) = (2, 128), (4, 256),(8, 512)IF (SRC2 *is memory*) (AND EVEX.b = 1)THEN FOR j := 0 TO KL-1i := j * 64src[i+63:i] := SRC2[63:0]ENDFOR;ELSE src := SRC2FI; Concatenate sourcestmp[VL-1:0] := src[VL-1:0]tmp[2VL-1:VL] := SRC1[VL-1:0]; Shift right quadword elementsIF VL = 128THEN SHIFT = imm8[0]ELSE IF VL = 256THEN SHIFT = imm8[1:0]ELSE SHIFT = imm8[2:0]FIFI;tmp[2VL-1:0] := tmp[2VL-1:0] >> (64*SHIFT); Apply writemaskFOR j := 0 TO KL-1i := j * 64IF k1[j] OR *no writemask*THEN DEST[i+63:i] := tmp[i+63:i]ELSE IF *merging-masking*; merging-maskingTHEN *DEST[i+63:i] remains unchanged*ELSE ; zeroing-maskingDEST[i+63:i] := 0FIFI;ENDFOR;DEST[MAXVL-1:VL] := 0

image/svg+xmlIntel C/C++ Compiler Intrinsic EquivalentVALIGND __m512i _mm512_alignr_epi32( __m512i a, __m512i b, int cnt);VALIGND __m512i _mm512_mask_alignr_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b, int cnt);VALIGND __m512i _mm512_maskz_alignr_epi32( __mmask16 k, __m512i a, __m512i b, int cnt);VALIGND __m256i _mm256_mask_alignr_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b, int cnt);VALIGND __m256i _mm256_maskz_alignr_epi32( __mmask8 k, __m256i a, __m256i b, int cnt);VALIGND __m128i _mm_mask_alignr_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b, int cnt);VALIGND __m128i _mm_maskz_alignr_epi32( __mmask8 k, __m128i a, __m128i b, int cnt);VALIGNQ __m512i _mm512_alignr_epi64( __m512i a, __m512i b, int cnt);VALIGNQ __m512i _mm512_mask_alignr_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b, int cnt);VALIGNQ __m512i _mm512_maskz_alignr_epi64( __mmask8 k, __m512i a, __m512i b, int cnt);VALIGNQ __m256i _mm256_mask_alignr_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b, int cnt);VALIGNQ __m256i _mm256_maskz_alignr_epi64( __mmask8 k, __m256i a, __m256i b, int cnt);VALIGNQ __m128i _mm_mask_alignr_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b, int cnt);VALIGNQ __m128i _mm_maskz_alignr_epi64( __mmask8 k, __m128i a, __m128i b, int cnt);ExceptionsSee Table2-50, “Type E4NF Class Exception Conditions”.

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