V4FMADDPS/V4FNMADDPS — Packed Single-Precision Floating-Point Fused Multiply-Add (4-iterations)Instruction Operand EncodingDescriptionThis instruction computes 4 sequential packed fused single-precision floating-point multiply-add instructions with a sequentially selected memory operand in each of the four steps.In the above box, the notation of “+3” is used to denote that the instruction accesses 4 source registers based on that operand; sources are consecutive, start in a multiple of 4 boundary, and contain the encoded register operand.This instruction supports memory fault suppression. The entire memory operand is loaded if any of the 16 lowest significant mask bits is set to 1 or if a “no masking” encoding is used.The tuple type Tuple1_4X implies that four 32-bit elements (16 bytes) are referenced by the memory operation portion of this instruction.Rounding is performed at every FMA (fused multiply and add) boundary. Exceptions are also taken sequentially. Pre- and post-computational exceptions of the first FMA take priority over the pre- and post-computational excep-tions of the second FMA, etc.Opcode/InstructionOp/En64/32 bit Mode SupportCPUID Feature FlagDescriptionEVEX.512.F2.0F38.W0 9A /rV4FMADDPS zmm1{k1}{z}, zmm2+3, m128AV/VAVX512_4FMAPSMultiply packed single-precision floating-point values from source register block indicated by zmm2 by values from m128 and accumulate the result in zmm1.EVEX.512.F2.0F38.W0 AA /rV4FNMADDPS zmm1{k1}{z}, zmm2+3, m128AV/VAVX512_4FMAPSMultiply and negate packed single-precision floating-point values from source register block indicated by zmm2 by values from m128 and accumulate the result in zmm1.Op/EnTupleOperand 1Operand 2Operand 3Operand 4ATuple1_4XModRM:reg (r, w)EVEX.vvvv (r)ModRM:r/m (r)NA
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