UNPCKHPD—Unpack and Interleave High Packed Double-Precision Floating-Point ValuesInstruction Operand EncodingDescriptionPerforms an interleaved unpack of the high double-precision floating-point values from the first source operand and the second source operand. See Figure 4-15 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be enforced.VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed. VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The destina-tion operand is a ZMM register, conditionally updated using writemask k1. EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register, a 256-bit memory location, or a 256-bit vector broadcasted from a 64-bit memory location. The destina-tion operand is a YMM register, conditionally updated using writemask k1. EVEX.128 encoded version: The first source operand is a XMM register. The second source operand is a XMM register, a 128-bit memory location, or a 128-bit vector broadcasted from a 64-bit memory location. The destina-tion operand is a XMM register, conditionally updated using writemask k1. Opcode/InstructionOp / En64/32 bit Mode SupportCPUID Feature FlagDescription66 0F 15 /rUNPCKHPD xmm1, xmm2/m128AV/VSSE2Unpacks and Interleaves double-precision floating-point values from high quadwords of xmm1 and xmm2/m128.VEX.128.66.0F.WIG 15 /rVUNPCKHPD xmm1,xmm2, xmm3/m128BV/VAVXUnpacks and Interleaves double-precision floating-point values from high quadwords of xmm2 and xmm3/m128.VEX.256.66.0F.WIG 15 /rVUNPCKHPD ymm1,ymm2, ymm3/m256BV/VAVXUnpacks and Interleaves double-precision floating-point values from high quadwords of ymm2 and ymm3/m256.EVEX.128.66.0F.W1 15 /rVUNPCKHPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcstCV/VAVX512VLAVX512FUnpacks and Interleaves double precision floating-point values from high quadwords of xmm2 and xmm3/m128/m64bcst subject to writemask k1.EVEX.256.66.0F.W1 15 /rVUNPCKHPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcstCV/VAVX512VLAVX512FUnpacks and Interleaves double precision floating-point values from high quadwords of ymm2 and ymm3/m256/m64bcst subject to writemask k1.EVEX.512.66.0F.W1 15 /rVUNPCKHPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcstCV/VAVX512FUnpacks and Interleaves double-precision floating-point values from high quadwords of zmm2 and zmm3/m512/m64bcst subject to writemask k1.Op/EnTuple TypeOperand 1Operand 2Operand 3Operand 4ANAModRM:reg (r, w)ModRM:r/m (r)NANABNAModRM:reg (w)VEX.vvvv (r)ModRM:r/m (r)NACFullModRM:reg (w)EVEX.vvvv (r)ModRM:r/m (r)NA
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