UMWAIT—User Level Monitor Wait Instruction Operand Encoding1DescriptionUMWAIT instructs the processor to enter an implementation-dependent optimized state while monitoring a range of addresses. The optimized state may be either a light-weight power/performance optimized state or an improved power/performance optimized state. The selection between the two states is governed by the explicit input register bit[0] source operand.UMWAIT is available when CPUID.7.0:ECX.WAITPKG[bit 5] is enumerated as 1. UMWAIT may be executed at any privilege level. This instruction’s operation is the same in non-64-bit modes and in 64-bit mode.The input register contains information such as the preferred optimized state the processor should enter as described in the following table. Bits other than bit 0 are reserved and will result in #GP if nonzero.The instruction wakes up when the time-stamp counter reaches or exceeds the implicit EDX:EAX 64-bit input value (if the monitoring hardware did not trigger beforehand).Prior to executing the UMWAIT instruction, an operating system may specify the maximum delay it allows the processor to suspend its operation. It can do so by writing TSC-quanta value to the following 32bit MSR (IA32_UMWAIT_CONTROL at MSR index E1H):•IA32_UMWAIT_CONTROL[31:2] — Determines the maximum time in TSC-quanta that the processor can reside in either C0.1 or C0.2. A zero value indicates no maximum time. The maximum time value is a 32-bit value where the upper 30 bits come from this field and the lower two bits are zero.•IA32_UMWAIT_CONTROL[1] — Reserved.•IA32_UMWAIT_CONTROL[0] — C0.2 is not allowed by the OS. Value of “1” means all C0.2 requests revert to C0.1.If the processor that executed a UMWAIT instruction wakes due to the expiration of the operating system time-limit, the instructions sets RFLAGS.CF; otherwise, that flag is cleared.The UMWAIT instruction causes a transactional abort when used inside a transactional region.The UMWAIT instruction operates with the UMONITOR instruction. The two instructions allow the definition of an address at which to wait (UMONITOR) and an implementation-dependent optimized operation to perform while waiting (UMWAIT). The execution of UMWAIT is a hint to the processor that it can enter an implementation-depen-dent-optimized state while waiting for an event or a store operation to the address range armed by UMONITOR. The UMWAIT instruction will not wait (will not enter an implementation-dependent optimized state) if any of the Opcode /InstructionOp/ En64/32 bit Mode SupportCPUID Feature FlagDescriptionF2 0F AE /6UMWAIT r32, <edx>, <eax>AV/VWAITPKGA hint that allows the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events.Op/EnTupleOperand 1Operand 2Operand 3Operand 4ANAModRM:r/m (r)NANANA1.The Mod field of the ModR/M byte must have value 11B.Table 4-26. UMWAIT Input Register Bit DefinitionsBit ValueState NameWakeup TimePower SavingsOther Benefitsbit[0] = 0C0.2SlowerLargerImproves performance of the other SMT thread(s) on the same core.bit[0] = 1C0.1FasterSmallerNAbits[31:1]NANANAReserved
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